H. Hidaka
发表
A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM
K. Arimoto,
M. Asakura,
T. Oishi,
1993,
Symposium 1993 on VLSI Circuits.
Cell-Plate Line Connecting Complementary Bitline (c/sup 3/) Architecture For Battery Operating DRAMs
K. Fujishima,
K. Arimoto,
H. Hidaka,
1991,
1991 Symposium on VLSI Circuits.
K. Fujishima,
K. Arimoto,
H. Hidaka,
1990,
Digest of Technical Papers., 1990 Symposium on VLSI Circuits.
H. Hidaka,
2002
.
K. Fujishima,
H. Hidaka,
Y. Matsuda,
1990,
Digest of Technical Papers., 1990 Symposium on VLSI Circuits.
K. Arimoto,
M. Asakura,
S. Tomishima,
1993,
Symposium 1993 on VLSI Circuits.
H. Hidaka,
J. Barth,
2005,
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..