Tetsuya Hirose

发表

An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems

Nobutaka Kuroki, Kaori Matsumoto, Tetsuya Hirose, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

An Error Diagnosis Technique Based on Clustering of Elements

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2021, IEICE Trans. Inf. Syst..

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, 2007 International Joint Conference on Neural Networks.

An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2015, IEICE Trans. Electron..

Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications

Tetsuya Hirose, 2011, 2011 International SoC Design Conference.

Write-assisted subthreshold SRAM by using on-chip threshold voltage monitoring circuit

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

A 0.1–0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2020, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 1-$\mu\hbox{W}$ 600- $\hbox{ppm}/^{\circ}\hbox{C}$ Current Reference Circuit Consisting of Subthreshold CMOS Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation

Masanori Hashimoto, Takao Onoye, Igors Homjakovs, 2013, IEICE Electron. Express.

A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Super-Resolution with Four Parallel Convolutional Neural Networks

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2016 .

An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting

Nobutaka Kuroki, Takanori Sato, Tetsuya Hirose, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, IEICE Electron. Express.

A MOS circuit for bursting neural oscillators with excitable oregonators

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004, IEICE Electron. Express.

A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2018, IEICE Trans. Electron..

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2013, IEEE Journal of Solid-State Circuits.

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, IEICE Electron. Express.

A CMOS bandgap and sub-bandgap voltage reference circuits for nanowatt power LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, 2004 .

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, IEICE Trans. Electron..

C-010 A Hardware Architecture to Perform K-means Clustering for Learning-Based Super-Resolution Combining Self-Learning and Prior-Learning Dictionaries

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2015 .

Ultralow-Power Current Reference Circuit with Low Temperature Dependence

Tetsuya Asai, Toshimasa Matsuoka, Kenji Taniguchi, 2005, IEICE Trans. Electron..

Critical temperature sensor based on oscillatory neuron models (Special issue on nonlinear circuits and signal processing)

Tetsuya Asai, Tetsuya Hirose, Gessyca Maria Tovar, 2008 .

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, 2011 IEEE 9th International New Circuits and systems conference.

A low-power single-slope analog-to-digital converter with digital PVT calibration

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

A Wireless Power Transfer System for Small-Sized Sensor Applications

Masanori Hashimoto, Nobutaka Kuroki, Masahiro Numa, 2015 .

Dedicated antenna less power efficient OOK transmitter for mm-cubic IoT nodes

Masanori Hashimoto, Tetsuya Hirose, Ryo Shirai, 2017, 2017 47th European Microwave Conference (EuMC).

Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2015, IEICE Electron. Express.

A Competitive Neural Network with Neuromorphic Single-Electron Circuits

Tetsuya Asai, Tetsuya Hirose, Takahide Oya, 2003 .

Precisely-timed synchronization among spiking neural circuits on analog VLSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004 .

Highly-efficient power transmitter coil design for small wireless sensor nodes

Masanori Hashimoto, Nobutaka Kuroki, Tetsuya Hirose, 2016, 2016 International Symposium on Antennas and Propagation (ISAP).

Combination of Convolutional Neural Network Architecture and its Learning Method for Rotation‐Invariant Handwritten Digit Recognition

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2020 .

Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Analytical study of rectifier circuit for wireless power transfer systems

Masanori Hashimoto, Nobutaka Kuroki, Tetsuya Hirose, 2016, 2016 International Symposium on Antennas and Propagation (ISAP).

Detecting Tampered Region in video using LSTM and U-Net

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2020 .

Neuromorphic MOS Circuits Implementing a Temporal Coding Neural Model

Tetsuya Asai, Tetsuya Hirose, Daichi Fujita, 2008 .

Spiking neuron devices consisting of single-flux-quantum circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, ICONIP.

A CMOS IF Variable Gain Amplifier with Exponential Gain Control

Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Hirose, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Pulsed Neural Networks Consisting of Single-Flux-Quantum Spiking Neurons

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007 .

Detecting tampered regions in JPEG images via CNN

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS).

Super-resolution technique for thermography with dual-camera system

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, Int. J. Bifurc. Chaos.

Process Compensation Techniques for Low-Voltage CMOS Digital Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009 .

Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter

Nobutaka Kuroki, Masahiro Numa, Daisuke Kanemoto, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control

Akira Tada, Tetsuya Hirose, Masahiro Numa, 2009, IEICE Electron. Express.

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2005, Int. J. Unconv. Comput..

Image super-resolution with multi-channel convolutional neural networks

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Multi-Channel Convolutional Neural Networks for Image Super-Resolution

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2010, IEICE Trans. Electron..

A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems

Akihiko Konagaya, Tsutomu Maruyama, Tetsuya Hirose, 1993, ICGA.

Message Passing Communication in a Parallel Computer Cenju-4

Toshiyuki Nakata, Tetsuya Hirose, Takeo Hosomi, 1999, ISHPC.

A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Highly Sensitive Thermosensing CMOS Circuit Based on Self-Biasing Circuit Technique

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009 .

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, Int. J. Bifurc. Chaos.

Single-flux-quantum circuits for spiking neuron devices

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006 .

An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Precisely-timed synchronization among spiking neuron circuits on silicon neural networks - Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP learning units

Tetsuya Asai, Alexandre Schmid, Tetsuya Hirose, 2005 .

A 18.9-nA standby current comparator with adaptive bias current generator

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters

Tetsuya Asai, Tetsuya Hirose, Kazuki Nakada, 2007, Neurocomputing.

Noise-Induced Phase Synchronization among Nonidentical Analog CMOS Oscillators

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008 .

Nano-ampere CMOS current reference with little temperature dependence using small offset voltage

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Architecture of a parallel machine: Cenju-3

Yu Inamura, Tsutomu Maruyama, Tetsuya Hirose, 1995, Systems and Computers in Japan.

Atomic configuration of boron pile-up at the Si/SiO2 interface

Hiroshi Tsuji, Kenji Taniguchi, Tetsuya Hirose, 2004, IEICE Electron. Express.

Detecting tampered region in video using LSTM and U‐Net

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2020 .

A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2014, IEICE Trans. Electron..

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A-1-12 Low-voltage Operation of Master-Slave Flip-Flops

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007 .

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2004, IEICE Electron. Express.

Neuromorphic MOS Circuits Exhibiting Precisely Timed Synchronization with Silicon Spiking Neurons and Depressing Synapses (Special Issue on Nonlinear Circuits and Signal Processing)

Tetsuya Asai, Tetsuya Hirose, Gessyca Maria Tovar, 2006 .

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2011, IEICE Trans. Electron..

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2012, IEEE Journal of Solid-State Circuits.

A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting

Nobutaka Kuroki, Masahiro Numa, Daisuke Kanemoto, 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS).

A DSM architecture for a parallel computer Cenju-4

Tetsuya Hirose, Takeo Hosomi, Masaaki Nakamura, 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes

Masanori Hashimoto, Yuichi Itoh, Tetsuya Hirose, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Signal-dependent analog-to-digital converter based on MINIMAX sampling

Masanori Hashimoto, Takao Onoye, Igors Homjakovs, 2011, 2012 International SoC Design Conference (ISOCC).

Impedance matching in magnetic-coupling-resonance wireless power transfer for small implantable devices

Masanori Hashimoto, Nobutaka Kuroki, Tetsuya Hirose, 2017, 2017 IEEE Wireless Power Transfer Conference (WPTC).

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment

Shintaro Izumi, Masahiko Yoshimoto, Ippei Akita, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Locally Weighted Averaging for Denoising of Medical Tomographic Images

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2016 .

A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Noise-shaping pulse-density modulation in inhibitory neural networks with subthreshold neuron circuits

Tetsuya Asai, Tetsuya Hirose, Akira Utagawa, 2007 .

Neuronal synchrony detection on single-electron neural networks

Tetsuya Asai, Tetsuya Hirose, Takahide Oya, 2006 .

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009, ASP-DAC.

On Digital LSI Circuits Exploiting Collision-Based Fusion Gates

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008, Int. J. Unconv. Comput..

Low Voltage Operation of Master-Slave Flip-Flops for Ultra-Low Power Subthreshold LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008 .

Power-supply circuits for ultralow-power subthreshold MOS-LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, IEICE Electron. Express.

An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes

Masanori Hashimoto, Tetsuya Hirose, Ryo Shirai, 2018, 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS).

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2015, The 20th Asia and South Pacific Design Automation Conference.

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2010, 2010 Proceedings of ESSCIRC.

Super-Resolution with Multi-Path Convolutional Neural Networks

Nobutaka Kuroki, Masahiro Numa, Tetsuya Hirose, 2020 .

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling

Masanori Hashimoto, Takao Onoye, Igors Homjakovs, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

H-029 Layout Recognition of Objects and Labels Based on Combination Optimization Algorithm

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2012 .

Neuromorphic Single-Electron Circuit and its Application to Temporal-Domain Neural Competition

Tetsuya Asai, Tetsuya Hirose, Takahide Oya, 2004 .

Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node

Masanori Hashimoto, Tetsuya Hirose, Ryo Shirai, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Noise-Induced Synchronization among Sub-RF CMOS Neural Oscillators for Skew-Free Clock Distribution

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2007 .

A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application

Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2008 .

Temperature-compensated nano-ampere current reference circuit with subthreshold metal-oxide-semiconductor field-effect transistor resistor ladder (Special issue: Solid state devices and materials)

Nobutaka Kuroki, Tetsuya Hirose, Yuji Osaki, 2011 .

Floating Millivolt Reference for PTAT Current Generation in Subthreshold MOS LSIs

Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya, 2009 .

Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting

Nobutaka Kuroki, Tetsuya Hirose, Hiroki Asano, 2016, IEEE Journal of Solid-State Circuits.