Tsuyoshi Iwagaki

发表

Reducibility of sequential test generation to combinational test generation for several delay fault models

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2003, 2003 Test Symposium.

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties

Tsuyoshi Iwagaki, Mineo Kaneko, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

A Low Power Deterministic Test Using Scan Chain Disable Technique

Hideo Fujiwara, Tsuyoshi Iwagaki, Michiko Inoue, 2006, IEICE Trans. Inf. Syst..

State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Studies on Design for Delay Testability and Delay Test Generation for Sequential Circuits

Tsuyoshi Iwagaki, 2004 .

State assignment for fault tolerant stochastic computing with linear finite state machines

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2017, 2017 International Test Conference in Asia (ITC-Asia).

A practical approach for logic simplification based on fault acceptability for error tolerant application

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2015, 2015 20th IEEE European Test Symposium (ETS).

Efficient path delay test generation based on stuck-at test generation using checker circuitry

Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, 2007, ICCAD 2007.

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer

Tsuyoshi Iwagaki, Mineo Kaneko, Eiri Takeda, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation

Hideo Fujiwara, Tsuyoshi Iwagaki, Michiko Inoue, 2005, 14th Asian Test Symposium (ATS'05).

Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines

Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue, 2020, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)

Tsuyoshi Iwagaki, Mineo Kaneko, 2008 .

A design methodology to realize delay testable controllers using state transition information

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Logic simplification by minterm complement for error tolerant application

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test

Yuki Fukazawa, Tsuyoshi Iwagaki, Tomoo Inoue, 2013, 2013 22nd Asian Test Symposium.

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Safe clocking register assignment in datapath synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008, 2008 IEEE International Conference on Computer Design.

A design scheme for delay fault testability of controllers using state transition information

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara, 2003 .

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Efficient path delay test generation based on stuck-at test generation using checker circuitry

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2005, European Test Symposium (ETS'05).

Designing area-efficient controllers for multi-cycle transient fault tolerant systems

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2015, 2015 20th IEEE European Test Symposium (ETS).

A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs

Tsuyoshi Iwagaki, Mineo Kaneko, 2009 .

Compact and Accurate Digital Filters Based on Stochastic Computing

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2019, IEEE Transactions on Emerging Topics in Computing.

Safe clocking for the setup and hold timing constraints in datapath synthesis

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2009, GLSVLSI '09.

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations

Kewal K. Saluja, Tsuyoshi Iwagaki, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation

Hideo Fujiwara, Tsuyoshi Iwagaki, Satoshi Ohtake, 2006, VLSI-SoC.

Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints

Keisuke Inoue, Tsuyoshi Iwagaki, Mineo Kaneko, 2008 .

Modeling economics of LSI design and manufacturing for test design selection

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation

Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, 2007 .

Compact and accurate stochastic circuits with shared random number sources

Tsuyoshi Iwagaki, Tomoo Inoue, Hideyuki Ichihara, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).