Yasuo Inoue

发表

Deaminoneuraminidase and manufacturing processes for

Sadako Inoue, Yasuo Inoue, Ken Kitajima, 1995 .

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

SOI DRAM: its features and possibility

Yasuo Yamaguchi, Yasuo Inoue, 1995, 1995 IEEE International SOI Conference Proceedings.

A 21-mW 4-Mb CMOS SRAM for battery operation

M. Ukita, Kenji Anami, O. Sakamoto, 1991 .

Hot-Carrier Reliability in Submicrometer Ultra-Thin SOI-MOSFET's

Masahiro Shimizu, Tadashi Nishimura, Katsuhiro Tsukamoto, 1992 .

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Hideto Hidaka, Kazuyasu Fujishima, T. Iwamatsu, 1994 .

Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect

Jun Takahashi, Toshiaki Iwamatsu, Tadashi Nishimura, 1995 .

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)

Fukashi Morishita, Kazutami Arimoto, Michihiro Yamada, 1999 .

Correction circuit for error code

Shoji Ueno, Yasuo Inoue, Yasuhiro Yamada, 1987 .

Practical Application and Fundamental Principle for Prevention of Noise and Low-Frequency Sound Problem

Yasuo Inoue, Y. Inoue, 2012 .

Duennfilmfeldeffektelement and manufacturing method thereof

Tadashi Nishimura, Yasuo Inoue, Motoi Ashida, 1992 .

An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits

Tsutomu Hirao, Koichiro Mashiko, Takashi Iwamatsu, 1995, 1995 IEEE International SOI Conference Proceedings.

A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

Shigenobu Maeda, Shigeto Maegawa, Natsuro Tsubouchi, 1995 .

Comparison of self-heating effect (SHE) in short-channel bulk and ultra-thin BOX SOI MOSFETs: Impacts of doped well, ambient temperature, and SOI/BOX thicknesses on SHE

Ken Uchida, Takahiro Shinada, Yasuo Inoue, 2013, 2013 IEEE International Electron Devices Meeting.

Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Shigenobu Maeda, Toshiaki Iwamatsu, Shigeto Maegawa, 2002, Digest. International Electron Devices Meeting,.

Electrical Characteristics and Crystal Quality Analysis of Thin-Body Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

Hidekazu Oda, Toshiaki Iwamatsu, Yasuo Inoue, 2009 .

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

Masahide Inuishi, Shigeto Maegawa, Yasuo Inoue, 2003 .

Study of Stress from Discontinuous SiN Liner for Fully-Silicided Gate Process

Takeshi Okagaki, Tomohiro Yamashita, Hidekazu Oda, 2007 .

A Study of Short Channel Behavior of Accumulation Type SOI MOSFETs

Yasuo Inoue, N. Tsubouchi, Yasuo Yamaguchi, 1993 .

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

T. Iwamatsu, Yasuo Inoue, N. Tsubouchi, 1995 .