K. Yamashita

HiSIM: a MOSFET model for circuit simulation connecting circuit performance with technology

H.J. Mattausch, S. Kumashiro, M. Miura-Mattausch, 2002, Digest. International Electron Devices Meeting,.

Interconnect scaling scenario using a chip level interconnect model

K. Yamashita, S. Odanaka, 2000 .

150-Mbit/s, 600-Mbit/s, and 2.4-Gbit/s optical interface modules for SDH transmission systems

Y. Yamada, K. Yamashita, K. Harada, 1994 .