S. Areibi

Parallel Processing on FPGAs: The Effect of Profiling on Performance

Xiaoguang Li, S. Areibi, R. Dony, 2006, 2006 6th International Workshop on System on Chip for Real Time Applications.

Congestion driven placement for VLSI standard cell design

Zhen Yang, S. Areibi, 2003, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).

A Hardware/Software Co-Design Approach for VLSI Circuit Partitioning

Fujian Li, S. Areibi, 2006, 2006 6th International Workshop on System on Chip for Real Time Applications.

A comparison of ILP based global routing models for VLSI ASIC design

Zhen Yang, A. Vannelli, S. Areibi, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

Hierarchical FPGA placement

G. Grewal, P. Du, S. Areibi, 2007, Canadian Journal of Electrical and Computer Engineering.

A hardware/software co-design approach for face recognition

Xiaoguang Li, S. Areibi, S. Areibi, 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

A Machine Learning Approach to Predict Timing Delays During FPGA Placement

S. Areibi, G. Grewal, T. Martin, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

S. Areibi, M. Anis, M. Elmasry, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

A Comparison of Heuristics for FPGA Placement

X. Bao, S. Areibi, G. Grewal, 2006 .

An efficient rectilinear Steiner tree algorithm for VLSI global routing

A. Vannelli, S. Areibi, M. Xie, 2001, Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555).