Darren L. Anand

Shared fuse macro for multiple embedded memory devices with redundancy

Michael R. Ouellette, Darren L. Anand, P. Jakobsen, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

John E. Barth, R. Houghton, S. Burns, 2003 .

A Multi-Time Programmable Memory Technology in a Native 14nm FINFET Process using Charge Trap Transistors (CTTs)

Toshiaki Kirihata, Sebastian Ventrone, Faraz Khan, 2019 .