Kenji Takahashi

发表

300 mm wafer-level hybrid bonding for Cu/interlayer dielectric bonding in vacuum

K. Kikuchi, Kenji Takahashi, M. Fujino, 2019, Japanese Journal of Applied Physics.

Micro Cu Bump Interconnection on 3D Chip Stacking Technology

Y. Tomita, Kenji Takahashi, K. Tanida, 2004 .

Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications

Morihiro Kada, Kenji Takahashi, Kazuo Kondo, 2015 .

Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

Kazumasa Tanida, Mitsuo Umemoto, Yoshihiro Tomita, 2003 .

Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 µm Pitch

M. Tago, Y. Tomita, Y. Akiyama, 2003 .

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Hideo Hosono, Masahiro Hirano, Kenji Nomura, 2007 .

Operation model with carrier-density dependent mobility for amorphous In–Ga–Zn–O thin-film transistors

T. Kamiya, K. Nomura, H. Hosono, 2012 .

Mobility- and temperature-dependent device model for amorphous In–Ga–Zn–O thin-film transistors

T. Kamiya, H. Hosono, A. Sato, 2014 .

Marked Response to Radio-frequency Hyperthermia in a Patient Having Back Pain with No Evidence of Magnetic Resonance Imaging Abnormalities

H. Kurosaki, Kenji Takahashi, Shinji Mori, 2010 .

Current Status of Research and Development for Three-Dimensional Chip Stack Technology

Manabu Bonkohara, Yoshihiro Tomita, Y. Yamaji, 2001 .

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

S. Oh, K. Kondo, J. Sun, 2003 .

High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking II. Reduced Electrodeposition Process Time

K. Kondo, D. Barkey, D. Mikami, 2005 .

Copper Via Filling Electrodeposition of High Aspect Ratio Through Chip Electrodes Used for the Three Dimensional Packaging

Seung Jin Oh, M. Tomisaka, Hitoshi Yonemura, 2003 .

3D Chip Stacking Utilizing 20 μm-Pitch Micro Cu Bump Interconnection

Kenji Takahashi, K. Tanida, M. Umemoto, 2005 .