L. Economikos

发表

L. Economikos, T. Morrison, F. Crnic, 1994 .

Computer vision for automatic inspection of a high density grid of pads on multi-chip modules (MCM-D)

J. Lambright, L. Economikos, M. E. Seaman, 1994 .

Structural demonstration of cost effective isolation trench fill for sub-110 nm vertical trench DRAM and SOC applications

L. Economikos, Byeong Y. Kim, A. Guliani, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Enabling Scatterometry as an In-Line Measurement Technique for 32 nm BEOL Application

L. Economikos, M. G. Faruk, S. Zangooie, 2011, IEEE Transactions on Semiconductor Manufacturing.

Applications of Latent Open Test

L. Economikos, Shinwu Chiang, A. Halperin, 1994, Proceedings of the International Conference on Multichip Modules.

Computer vision for automatic inspection of complex metal patterns on multichip modules (MCM-D)

L. Economikos, M. E. Scaman, 1995 .

Technologies for scaling vertical transistor DRAM cells to 70 nm

C. Radens, R. Jammy, G. Bronner, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

9:20-9:40 "A Case Study for Fixed Abrasives in CMP: Production Acceptance of a New Technology through Performance, Persistence and Partnerships,"

J. Kim, L. Economikos, Sriram Anjur, 2006 .

High performance bulk planar 20nm CMOS technology for low power mobile applications

O. Menut, Y. Liu, S. Samavedam, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

U. Gruening, D. Casarotto, J. Alsmeier, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Open repair technologies for MCM-D

Thomas A. Wassick, L. Economikos, 1995 .

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

R. Augur, G. Biery, S. Arai, 2006, 2006 International Electron Devices Meeting.

Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology

L. Economikos, S. Tsai, Y. Moon, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

L. Economikos, Jianping Zheng, J. Muncy, 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology

Carl J. Radens, L. Economikos, C. Radens, 2000, 2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology - 2000 (Cat. No.00EX432).

Study of arsenic out-diffusion for buried plate formation in trench capacitors

L. Economikos, R. W. Young, C. S. Murthy, 1998, Twenty Third IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.98CH36205).

A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

W. Bergner, W. Mueller, J. Beintner, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond

W. Mueller, K. Varn, R. Jammy, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Investigation of CVD SiCOH low-k time-dependent dielectric breakdown at 65nm node technology

J. Gill, M. Shinosky, T. Ema, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..