Horng-Chih Lin

发表

Fabrication and characterization of a novel suspended-nanowire-channel thin-film transistor with nanometer air gap

Chia-Wei Hsu, Chia-Hao Kuo, Hsing-Hui Hsu, 2011, 2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

Anything more than size in nanoelectronics

Horng-Chih Lin, Wei-Xin Ni, Jia-Min Shieh, 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.

Characterization of plasma charging damage in ultrathin gate oxides

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

Mix-and-match lithography processes for 0.1-um MOS transistor device fabrication

Horng-Chih Lin, Tien-Sheng Chao, Kazumitsu Nakamura, 1996, Advanced Lithography.

Electrical characteristics of amorphous In-Ga-Zn-O thin-film transistors prepared by radio frequency magnetron sputtering with varying oxygen flows

Horng-Chih Lin, Cheng-I Lin, Yih-Shing Lee, 2014, Displays.

Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors

Yoon-Ha Jeong, Wen Liu, J.J. Liou, 2009, IEEE Electron Device Letters.

An Innovative Understanding of Metal–Insulator–Metal (MIM)-Capacitor Degradation Under Constant-Current Stress

You-Wen Yau, Horng-Chih Lin, A.S. Oates, 2007, IEEE Transactions on Device and Materials Reliability.

Temperature instability of amorphous In-Ga-Zn-O thin film transistors

Sheng-Kai Fan, Horng-Chih Lin, Chii-Wen Chen, 2013, 2013 6th IEEE/International Conference on Advanced Infocomm Technology (ICAIT).

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

Horng-Chih Lin, Tiao-Yuan Huang, Tien-Sheng Chao, 2010, Microelectron. Reliab..

P-11: A New Five-Mask-Count Process for Fabrication of Poly-Si Nanowire-Channel CMOS Inverters

Chia-Hao Kuo, Horng-Chih Lin, Tiao-Yuan Huang, 2012 .

High-gain, low-voltage BEOL logic gate inverter built with film profile engineered IGZO transistors

Horng-Chih Lin, Tiao-Yuan Huang, Pei-Wen Li, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Performance Improvement in RF LDMOS Transistors Using Wider Drain Contact

Guo-Wei Huang, Horng-Chih Lin, Tiao-Yuan Huang, 2013, IEEE Electron Device Letters.

使用I-Line雙重曝光技術實現非對稱0.1μm P型金氧半場效電晶體與相關可靠度問題之研究

Horng-Chih Lin, Tiao-Yuan Huang, 林鴻志, 2010 .

Reliability of ultrathin gate oxides for ULSI devices

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 1999 .

Relationships between the crystalline phase of an IGZO target and electrical properties of a-IGZO channel film

Horng-Chih Lin, Cheng-I Lin, Yih-Shing Lee, 2012 .

Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor

Horng-Chih Lin, Tiao-Yuan Huang, Keng-Ming Liu, 2012 .

Application of Field-Induced Source/Drain Schottky Metal-Oxide-Semiconductor to Fin-Like Body Field-Effect Transistor : semiconductors

Horng-Chih Lin, Tiao-Yuan Huang, Simon M. Sze, 2002 .

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 2000 .

A continuous semi-empiric transfer characteristics model for surrounding gate undoped polysilicon nanowire MOSFETs

Juin J. Liou, Adelmo Ortiz-Conde, Juan Muci, 2011 .

Impacts of SiN-Capping Layer on the Device Characteristics and Hot-Carrier Degradation of nMOSFETs

Horng-Chih Lin, Chia-Yu Lu, Yao-Jen Lee, 2007, IEEE Transactions on Device and Materials Reliability.

High-Performance Poly-Si Nanowire NMOS Transistors

Horng-Chih Lin, Chun-Jung Su, C. Su, 2007, IEEE Transactions on Nanotechnology.

Ambipolar Schottky barrier silicon-on-insulator metal oxide semiconductor transistors

Horng-Chih Lin, Tiao-Yuan Huang, Chia-Yu Lu, 2003 .

Impacts of uniaxial compressive strain on dynamic negative bias temperature instability of p-channel MOSFETs

Horng-Chih Lin, Tiao-Yuan Huang, Chia-Yu Lu, 2006 .

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Horng-Chih Lin, Tien-Sheng Chao, Tzu-I Tsai, 2011, IEEE Electron Device Letters.

Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels

Horng-Chih Lin, Tiao-Yuan Huang, Jung-Ruey Tsai, 2014 .

Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n -channel metal-oxide-semiconductor field-effect transistors with SiN capping

Horng-Chih Lin, Yao-Jen Lee, Ching-Sen Lu, 2007 .

A Model For Photoresist-induced Charging Damage In Ultra-thin Gate Oxides

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 1997, 2nd International Symposium on Plasma Process-Induced Damage.

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

Horng-Chih Lin, Tiao-Yuan Huang, Wu-Te Weng, 2009 .

The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs

Horng-Chih Lin, Tiao-Yuan Huang, Wen-Chin Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 1997 .

Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations

Hsing-Hui Hsu, Horng-Chih Lin, Tiao-Yuan Huang, 2008, IEEE Transactions on Electron Devices.

Poly-silicon nanowire field-effect transistor for ultrasensitive and label-free detection of pathogenic avian influenza DNA.

Horng-Chih Lin, Chih-Heng Lin, Fu-Hsiang Ko, 2009, Biosensors & bioelectronics.

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

Horng-Chih Lin, Tiao-Yuan Huang, Wen-Chin Lee, 2006, IEEE Electron Device Letters.

In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors

Horng-Chih Lin, Tiao-Yuan Huang, Yu-Chia Chang, 2010, IEEE Transactions on Electron Devices.

A Gate-All-Around Floating-Gate Memory Device with Triangular-Shaped Poly-Si Nanowire Channels

Horng-Chih Lin, Tiao-Yuan Huang, K. H. Lee, 2013 .

Characterization of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor

Horng-Chih Lin, Pei-Wen Li, You-Tai Chang, 2019, 2019 Silicon Nanoelectronics Workshop (SNW).

A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer

Horng-Chih Lin, Tiao-Yuan Huang, Ko-Hui Lee, 2013, IEEE Electron Device Letters.

Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel

Horng-Chih Lin, Tiao-Yuan Huang, Cheng-I Lin, 2012, IEEE Electron Device Letters.

Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide

Horng-Chih Lin, Tiao-Yuan Huang, Min-Yu Tsai, 2001 .

Evaluation of plasma charging damage in ultrathin gate oxides

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 1998 .

Process and doping species dependence of negative-bias-temperature instability for P-channel MOSFETs

Horng-Chih Lin, Tiao-Yuan Huang, Wan-Ju Chiang, 2002, 7th International Symposium on Plasma- and Process-Induced Damage.

Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

Hsing-Hui Hsu, Horng-Chih Lin, Horng-Chih Lin, 2009 .

Breakdown Modes and Their Evolution in Ultrathin Gate Oxide

Horng-Chih Lin, Tiao-Yuan Huang, Da-Yuan Lee, 2002 .