Yung-Shin Kao

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

Chien-Yu Lu, Shang-Lin Wu, Ming-Hsien Tu, 2016, Microelectron. J..

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Chien-Yu Lu, Hao-I Yang, Ming-Hsien Tu, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist

Ming-Hsien Tu, Kuen-Di Lee, Ching-Te Chuang, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.