M. Blyzniuk

How to increase ICs design productivity: one of the approaches

M. Blyzniuk, I. Kazymyra, 2002, Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542).

DEFECT ORIENTED FAULT COVERAGE OF 100% STUCK-AT FAULT TEST SETS

Witold A. Pleskacz, Wieslaw Kuzmicz, M. Blyzniuk, 2000 .

Estimation Of The Usefulness Of Test Vector Components For Detecting Faults Resulting From Shorts In Standard Cells M.

Witold A. Pleskacz, Wieslaw Kuzmicz, M. Lobur, 2000 .

Analysis of the approaches to dialogue system development and their realisation in interactive graphical schematic editor of "Micro-PC" circuit simulator

O. Markelov, M. Blyzniuk, 2001, Experience of Designing and Applications of CAD Systems in Microelectronics. Proceedings of the VI-th International Conference. CADSM 2001 (IEEE Cat. No.01 EX473).

Hierarchical defect-oriented fault simulation for digital circuits

R. Ubar, J. Raik, E. Gramatova, 2000, Proceedings IEEE European Test Workshop.

Models of ICs schematic vulnerability to local temperatures: development and analysis

M. Blyzniuk, I. Kazymyra, I. Farmaga, 2001, Experience of Designing and Applications of CAD Systems in Microelectronics. Proceedings of the VI-th International Conference. CADSM 2001 (IEEE Cat. No.01 EX473).

Estimation of parametric sensitivity for defects size distribution in VLSI defect/fault analysis

M. Blyzniuk, I. Kazymyra, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

Simplified Models of IC’S for the Acceleration of Circuit Design

Vladimir A. Koval, M. Blyzniuk, Irena Y. Kazymyra, 1998 .

IC schematic vulnerability to the temperature field distribution: Pre-layout estimation

M. Blyzniuk, I. Kazymyra, 2004, 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716).