T. Saeki

A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

M. Mitsuishi, T. Saeki, H. Iwaki, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

M. Mitsuishi, T. Saeki, H. Iwaki, 2000, IEEE Journal of Solid-State Circuits.

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

T. Matano, K. Yoshida, M. Fujita, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A remote console system for balloon borne experiments

Takamasa Yamagami, Mitsuaki Nozaki, Koji Yoshimura, 1992 .