Vinicius V. A. Camargo

Circuit simulation of workload-dependent RTN and BTI based on trap kinetics

Tibor Grasser, Ben Kaczer, Gilson I. Wirth, 2014, Microelectron. Reliab..

Recent trends in CMOS reliability: From individual traps to circuit simulations

Tibor Grasser, Ben Kaczer, Francky Catthoor, 2011 .

NBTI-aware technique for transistor sizing of high-performance CMOS gates

Gilson I. Wirth, Lucas Brusamarello, Vinicius V. A. Camargo, 2009, 2009 10th Latin American Test Workshop.

Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits

Tibor Grasser, Guido Groeseneken, Ben Kaczer, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.