N. Tzartzanis

发表

Differential current-mode sensing for efficient on-chip global signaling

N. Tzartzanis, W.W. Walker, 2005, IEEE Journal of Solid-State Circuits.

Energy recovery for the design of high-speed, low-power static RAMs

N. Tzartzanis, William C. Athas, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

N. Tzartzanis, W.W. Walker, K. Kanda, 2009, IEEE Journal of Solid-State Circuits.

A low-power microprocessor based on resonant energy

Lars Svensson, N. Tzartzanis, William C. Athas, 1997, IEEE J. Solid State Circuits.

A Reversible Poly-Phase Distributed VCO

N. Tzartzanis, W.W. Walker, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Clock-powered CMOS VLSI graphics processor for embedded display controller application

N. Tzartzanis, Athas, W. Mao, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

SOI for VLSI clock-powered processors

N. Tzartzanis, W. Athas, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Static Memory Design

N. Tzartzanis, 2006 .

A Leakage Current Replica Keeper for Dynamic Circuits

N. Tzartzanis, W.W. Walker, Y. Lih, 2006, IEEE Journal of Solid-State Circuits.

Clock-powered logic for a 50 MHz low-power RISC datapath

N. Tzartzanis, W.C. Athas, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

D. Yamazaki, N. Tzartzanis, W.W. Walker, 2005, IEEE Journal of Solid-State Circuits.

A resonant signal driver for two-phase, almost-non-overlapping clocks

N. Tzartzanis, William C. Athas, Lars Svensson, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

The design and implementation of a low-power clock-powered microprocessor

N. Tzartzanis, W. Mao, K. Chong, 2000, IEEE Journal of Solid-State Circuits.

A 34word x 64b 10R/6W write-through self-timed dual-supply-voltage register file

A. Inoue, N. Tzartzanis, William W. Walker, 2002 .

A 40–44 Gb/s 3$\times$ Oversampling CMOS CDR/1:16 DEMUX

N. Tzartzanis, W.W. Walker, H. Tamura, 2007, IEEE Journal of Solid-State Circuits.

Clock-Powered CMOS for Energy-Efficient Computing

N. Tzartzanis, William Athas, 2017 .

Timed Dual-Supply-Voltage Register File

N. Tzartzanis, Atsuki Inoue, Hoa Nguyen, 2002 .

A 34 word/spl times/64 b 10 R/6 W write-through self timed dual-supply-voltage register file

A. Inoue, N. Tzartzanis, W.W. Walker, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

SESSION 13 Multi Gb/s Serial Receivers

Hirotaka Tamura, Tadahiro Kuroda, Masaya Kibune, 2004 .

A low-power SRAM with resonantly powered data, address, word, and bit lines

N. Tzartzanis, W. Athas, L. Svensson, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

N. Tzartzanis, T. Yamamoto, S. Matsubara, 2009, 2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium.

A differential current-mode sensing method for high-noise-immunity, single-ended register files

N. Tzartzanis, W.W. Walker, W. Walker, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications

D. Yamazaki, N. Tzartzanis, W.W. Walker, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A Framework for Practical Low-Power Digital CMOS Systems Using Adiabatic-Switching Principles

N. Tzartzanis, Lars Svensson, William Athas, 1994 .