H. Nambu

Synonym hit RAM; a 500 MHz 1.5 ns CMOS SRAM macro with 576 b parallel comparison and parity check functions

Y. Fujimura, K. Higeta, R. Yamagata, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions

Y. Fujimura, K. Yamaguchi, K. Higeta, 2000, IEEE Journal of Solid-State Circuits.

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

M. Usami, K. Higeta, K. Yamaguchi, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

M. Yoshida, K. Higeta, T. Suzuki, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

M. Usami, K. Higeta, K. Yamaguchi, 2000, IEEE Journal of Solid-State Circuits.