Zainalabedin Navabi

Masoud Daneshtalab, Zainalabedin Navabi, Mohammad Reza Kakoee, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services

Masoud Daneshtalab, Zainalabedin Navabi, Mohammad Reza Kakoee, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

VHDL Based Symbolic Model Checker with Improved CTL Property Language

Zainalabedin Navabi, Hamid Shojai, Hadi Parandeh Afshar, 2004 .

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC

Alfredo Benso, Giorgio Di Natale, Paolo Prinetto, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Reliability in Application Specific Mesh-Based NoC Architectures

Paolo Prinetto, Zainalabedin Navabi, Fatemeh Refan, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Online self adjusting progressive age monitoring of timing variations

Paolo Prinetto, Mehdi Kamal, John McNeil, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A heuristic path selection method for small delay defects test

Mehdi Kamal, Zainalabedin Navabi, Paniz Foroutan, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Fault Simulation Applications and Methods

Zainalabedin Navabi, 2011 .

ESL design with RTL-verified predesigned abstract communication channels

Zainalabedin Navabi, Alexander S. Kamkin, Hamed Najafi Haghi, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

Verilog Digital System Design

Zainalabedin Navabi, 1999 .

Configurable architecture for memory BIST

Zainalabedin Navabi, Atieh Lotfi, Parisa Kabiri, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms

Amirali Ghofrani, Nastaran Nemati, Zainalabedin Navabi, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Hardware description in verilog: an overview

Zainalabedin Navabi, Z. Navabi, 2000 .

ESL design methodology for architecture exploration

Zainalabedin Navabi, Fatemeh Javaheri, 2010, 2010 East-West Design & Test Symposium (EWDTS).

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure

Armin Alaghi, Zainalabedin Navabi, Mahshid Sedghi, 2008, 2008 IEEE International Test Conference.

Digitizing for Computer-Aided Finite Element Model Generation—Part 1: The General Program

Zainalabedin Navabi, H. A. Kamel, 1980 .

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization

Zainalabedin Navabi, Samira Ahmadi Farsani, Katayoon Basharkhah, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Using VHDL for modeling and design of processing units

Zainalabedin Navabi, 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint pdf

Mahmood Fathy, M. H. Haghbayan, Zainalabedin Navabi, 2017, ArXiv.

A new structure for interconnect offline testing

Zainalabedin Navabi, Farimah Farahmandi, Shahrzad Keshavarz, 2013, East-West Design & Test Symposium (EWDTS 2013).

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure

Zainalabedin Navabi, Shahrzad Keshavarz, Amirreza Nekooei, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Test instruction set (TIS) for high level self-testing of CPU cores

Zainalabedin Navabi, Hadi Esmaeilzadeh, Saeed Shamshiri, 2004, 13th Asian Test Symposium.

A probabilistic approach for counterexample generation to aid design debugging

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2013, East-West Design & Test Symposium (EWDTS 2013).

IMPACT OF VLSI TECHNOLOGY ON THE HARDWARE DESIGN LANGUAGE AHPL.

Zainalabedin Navabi, M. Masud, W. J. Knapp, 1980 .

Real-time embedded emotional controller

Caro Lucas, Zainalabedin Navabi, Arash Arami, 2010, Neural Computing and Applications.

Transaction Level Formal Verification using Timed Automata

Hamid Noori, Amirali Ghofrani, Zainalabedin Navabi, 2010 .

An optimized BIST architecture for FPGA look-up table testing

Armin Alaghi, Zainalabedin Navabi, Mahnaz Sadoughi Yarandi, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Assertion based verification in TLM

Amirali Ghofrani, Zainalabedin Navabi, Fatemeh Javaheri, 2010, 2010 East-West Design & Test Symposium (EWDTS).

A mixed HDL/PLI test package

Majid Namaki-Shoushtari, Nastaran Nemati, Zainalabedin Navabi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Near-Optimal Node Selection Procedure for Aging Monitor Placement

Zainalabedin Navabi, Somayeh Sadeghi Kohan, Arash Vafaei, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Data compression for system-on-chip testing using ATE

Fabrizio Lombardi, Waleed Meleis, Zainalabedin Navabi, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Merit based directed random test generation (MDRTG) scheme for combinational circuits

Zainalabedin Navabi, Arezoo Kamran, Mohammad Saeed Jahangiry, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Generating test patterns for sequential circuits using random patterns by PLI functions

M. H. Haghbayan, Zainalabedin Navabi, Ramyar Saeedi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations

Mahmood Fathy, Armin Alaghi, Zainalabedin Navabi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Reliable NoC architecture utilizing a robust rerouting algorithm

Mahmood Fathy, Armin Alaghi, Zainalabedin Navabi, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

Zainalabedin Navabi, Sied Mehdi Fakhraie, Mohammad H. Tehranipour, 2004, J. Electron. Test..

Programmable Logic Devices

Zainalabedin Navabi, 2005 .

Improving polynomial datapath debugging with HEDs

Masahiro Fujita, Zainalabedin Navabi, Payman Behnam, 2014, 2014 19th IEEE European Test Symposium (ETS).

SystemAda: an ada based system-level hardware description language

Zainalabedin Navabi, Mahshid Sedghi, Negin Mahani, 2009, ALET.

TruncApp: A truncation-based approximate divider for energy efficient DSP applications

Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Hierarchical fault simulation using behavioral and gate level hardware models

Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Fault simulation for VHDL based test bench and BIST evaluation

Zainalabedin Navabi, Mina Zolfy, Shahrzad Mirkhani, 2001, Proceedings 10th Asian Test Symposium.

Processor Testing Using an ADL Description and Genetic Algorithms

Zainalabedin Navabi, Zohreh Karimi, Elham Safi, 2003, VLSI-SOC.

Digital System Test and Testable Design: Using HDL Models and Architectures

Zainalabedin Navabi, 2010 .

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements

Jaan Raik, Zainalabedin Navabi, Maksim Jenihhin, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Online Test Macro Scheduling and Assignment in MPSoC Design

M. H. Haghbayan, Zainalabedin Navabi, Seyyed Alireza Hoseini, 2011, 2011 Asian Test Symposium.

Self-Adjusting Monitor for Measuring Aging Rate and Advancement

Mehdi Kamal, Zainalabedin Navabi, Somayeh Sadeghi-Kohan, 2017, IEEE Transactions on Emerging Topics in Computing.

A Test Approach for Look-Up Table Based FPGAs

Zainalabedin Navabi, Ehsan Atoofian, 2006, Journal of Computer Science and Technology.

Automatic correction of certain design errors using mutation technique

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2014, 2014 19th IEEE European Test Symposium (ETS).

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams

Zainalabedin Navabi, Bijan Alizadeh, Pejman Lotfi-Kamran, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information

Zainalabedin Navabi, Morteza Ebrahimi, Z. Navabi, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An off-line MDSI interconnect BIST incorporated in BS 1149.1

Nasser Masoumi, Zainalabedin Navabi, Somayeh Sadeghi Kohan, 2014, 2014 19th IEEE European Test Symposium (ETS).

Fault and Defect Modeling

Zainalabedin Navabi, 2011 .

A high-level language for design and modeling of hardware

Zainalabedin Navabi, 1992, J. Syst. Softw..

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation

Zainalabedin Navabi, Farnaz Forooghifar, Somayeh Sadeghi Kohan, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing

Zainalabedin Navabi, Mohammad Hosseinabady, Atefe Dalirsani, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An Efficient CPU Architecture for DSP Processors

Zainalabedin Navabi, Morteza Fayyazi, Mohammad R. Movahedin, 2001 .

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment

Zainalabedin Navabi, Christoph Grimm, Carna Zivkovic, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Elements of VHDL for description of hardware: a tutorial view

Zainalabedin Navabi, 1990, Third Annual IEEE Proceedings on ASIC Seminar and Exhibit.

Design of SAYEH Processor

Zainalabedin Navabi, 2005 .

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

Mohammad Ebrahimi, Zainalabedin Navabi, Rezgar Sadeghi, 2020, IEEE Transactions on Computers.

Embedded test for processor and memory cores in system-on-chips

Zainalabedin Navabi, Mehrdad Nourani, M. R. Movahedin, 2003 .

A New Approach for Design and Verification of Transaction Level Models

Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Component modeling for reliability analysis by simulation

Zainalabedin Navabi, Bijan Alizadeh, 1997, Proceedings VHDL International Users' Forum. Fall Conference.

Enhanced TED: A New Data Structure for RTL Verification

Zainalabedin Navabi, Mehran Massoumi, Pejman Lotfi-Kamran, 2008, 21st International Conference on VLSI Design (VLSID 2008).

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm

Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

Reducing test power, time and data volume in SoC testing using selective trigger scan architecture

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Simulating faults of combinational IP core-based SOCs in a PLI environment

Fabrizio Lombardi, Zainalabedin Navabi, Pedram A. Riahi, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

A description style for automatic hardware synthesis

Zainalabedin Navabi, J. Spillane, 2014 .

PLD Based Design

Zainalabedin Navabi, 2005 .

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST

M. H. Haghbayan, Zainalabedin Navabi, Saeed Safari, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

VHDL: Modular Design and Synthesis of Cores and Systems, 3rd Edition

Zainalabedin Navabi, 2007 .

Application-specific power-aware mapping for reconfigurable NoC architectures

Amin Ghasemazar, Zainalabedin Navabi, Mehran Goli, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture

Zainalabedin Navabi, Hossein Sabaghian-Bidgoli, Seyed Ali Shahabi, 2014, Canadian Journal of Electrical and Computer Engineering.

HDLs evolve as they affect design methodology for a higher abstraction and a better integration

Zainalabedin Navabi, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching

David R. Kaeli, Zainalabedin Navabi, Morteza Fayyazi, 2003, PDPTA.

Hardware program simulator

Zainalabedin Navabi, 1978 .

Hardware Description in Verilog

Zainalabedin Navabi, 1999, The VLSI Handbook.

RTL datapath optimization using system-level transformations

Masahiro Fujita, Zainalabedin Navabi, Bijan Alizadeh, 2014, Fifteenth International Symposium on Quality Electronic Design.

Automatic Correction of Dynamic Power Management Architecture in Modern Processors

Zainalabedin Navabi, Bijan Alizadeh, Reza Sharafinejad, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment

Fabrizio Lombardi, Zainalabedin Navabi, Pedram A. Riahi, 2003, Embedded Systems and Applications.

Generating gate level two phase dynamic MOS logic from AHPL

Zainalabedin Navabi, 1985 .

Utilizing NOPs for online deterministic testing of simple processing cores

Zainalabedin Navabi, Rasoul Jafari, Elham Zahraei Salehi, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Power-aware online testing of manycore systems in the dark silicon era

Hannu Tenhunen, Pasi Liljeberg, Amir-Mohammad Rahmani, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Signature oriented model pruning to facilitate multi-threaded processors debugging

Zainalabedin Navabi, Fatemeh Refan, Bijan Alizadeh, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Virtual tester development using HDL/PLI

Nastaran Nemati, Zainalabedin Navabi, Somayeh Sadeghi Kohan, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Simultaneous reduction of dynamic and static power in scan structures

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad Hosseinabady, 2005, Design, Automation and Test in Europe.

Early prediction of timing critical instructions in pipeline processor

Zainalabedin Navabi, Morteza Soltani, Arash Fouman Ajirlou, 2016, 2016 15th Biennial Baltic Electronics Conference (BEC).

Efficient Simulation of AHPL

Zainalabedin Navabi, Fredrick J. Hill, 1979, 16th Design Automation Conference.

Back-annotation of gate-level power properties into system level descriptions

Zainalabedin Navabi, Najmeh Farajipour Ghohroud, 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

Stochastic testing of processing cores in a many-core architecture

Zainalabedin Navabi, Arezoo Kamran, 2016, Integr..

Property checking based on hierarchical integer

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

Zainalabedin Navabi, 2006 .

Extracting complete set of equations to analyze VHDL-AMS descriptions

Zainalabedin Navabi, Vahid Janfaza, Arezoo Kamran, 2013, East-West Design & Test Symposium (EWDTS 2013).

Synthesis of VLSI circuits from behavioral descriptions

Zainalabedin Navabi, J. Spillane, 1991 .

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling

Zainalabedin Navabi, Katayoon Basharkhah, Rezgar Sadeghi, 2019, 2019 IEEE European Test Symposium (ETS).

Low overhead DFT using CDFG by modifying controller

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2007, IET Comput. Digit. Tech..

Behavioral Level Modeling of Gate Level Loading Effects

Zainalabedin Navabi, 1991 .

System level hardware design and simulation with SystemAda

Zainalabedin Navabi, Negin Mahani, Parnian Mokri, 2008, EWDTS.

On-Chip Verification of NoCs Using Assertion Processors

Masoud Daneshtalab, Zainalabedin Navabi, Mohammad Reza Kakoee, 2007 .

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits

Zainalabedin Navabi, Farimah Farahmandi, Bijan Alizadeh, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

VERILOG Digital System Design: Analysis and Design of Digital Systems with Cdrom

Zainalabedin Navabi, 1999 .

Timing description languages

Zainalabedin Navabi, Naghmeh Karimi, 2016 .

ASIC and custom IC cell information representation

Zainalabedin Navabi, Naghmeh Karimi, 2016 .

System Level Design Languages

Zainalabedin Navabi, Shahrzad Mirkhani, 2006 .

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors

Maghsoud Abbaspour, Zainalabedin Navabi, Hasan Sohofi, 2007, FDL.

Low test application time resource binding for behavioral synthesis

Zainalabedin Navabi, Mohammad Hosseinabady, Pejman Lotfi-Kamran, 2007, TODE.

Describing controlling hardware in VHDL

Zainalabedin Navabi, J. Spillane, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Implementing a complete test tool set in VHDL

Zainalabedin Navabi, A. Peymandoust, 1997, Proceedings VHDL International Users' Forum. Fall Conference.

Built-In Predictors for Dynamic Crosstalk Avoidance

Zainalabedin Navabi, Rezgar Sadeghi, 2020, 2020 IEEE European Test Symposium (ETS).

Gate Level Combinational Design

Zainalabedin Navabi, 2005 .

A Practical Approach to Signal Coverage Computation in Symbolic Model Checking

Siamak Mohammadi, Majid Nabi, Zainalabedin Navabi, 2007 .

Facilitating testability of TLM FIFO: SystemC implementations

Paolo Prinetto, Zainalabedin Navabi, Homa Alemzadeh, 2010, 2010 East-West Design & Test Symposium (EWDTS).

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

Zainalabedin Navabi, Hadi Esmaeilzadeh, Saeed Shamshiri, 2005, 14th Asian Test Symposium (ATS'05).

Online periodic test mechanism for homogeneous many-core processors

Zainalabedin Navabi, Arezoo Kamran, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors

Abhijit Chatterjee, Miodrag Potkonjak, Adit D. Singh, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

An advanced method for synthesizing TLM2-based interfaces

Zainalabedin Navabi, Nadereh Hatami, Z. Navabi, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

Combination of Assertion and HSAT Methods For Automated Test Vectors Generation

Zainalabedin Navabi, Mostafa Naderi, 2005, FDL.

Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions

Zainalabedin Navabi, Mehran Massoumi, 1991, Simul..

Low power scheduling in high-level synthesis using dual-Vth library

Zainalabedin Navabi, Bijan Alizadeh, Samaneh Ghandali, 2015, Sixteenth International Symposium on Quality Electronic Design.

Code optimization for enhancing SystemC simulation time

Zainalabedin Navabi, Homa Alemzadeh, Soheil Aminzadeh, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults

Armin Alaghi, Zainalabedin Navabi, Mahshid Sedghi, 2008, J. Univers. Comput. Sci..

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware

Majid Namaki-Shoushtari, Zainalabedin Navabi, Parastoo Kamranfar, 2011, 2011 Asian Test Symposium.

A Selective Trigger Scan Architecture for VLSI Testing

Fabrizio Lombardi, Zainalabedin Navabi, Mohammad Hosseinabady, 2008, IEEE Transactions on Computers.

Design experience in TL modeling

Paolo Prinetto, Nastaran Nemati, Zainalabedin Navabi, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Prolonging lifetime of non-volatile last level caches with cluster mapping

Zainalabedin Navabi, Morteza Soltani, Mohammad Ebrahimi, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

Using integer equations to check PSL properties in RT level design

Zainalabedin Navabi, Bijan Alizadeh, 2004 .

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition

Masahiro Fujita, Zainalabedin Navabi, Bijan Alizadeh, 2015, IEEE Transactions on Computers.

A VPI-based combinational IP core module-based mixed level serial fault simulation and test generation methodology

Fabrizio Lombardi, Zainalabedin Navabi, Pedram A. Riahi, 2003, 2003 Test Symposium.

Logic Built-in Self-test

Zainalabedin Navabi, Z. Navabi, 2011 .

Functional testing approaches for “BIFST-able” tlm_fifo

Paolo Prinetto, Stefano Di Carlo, Zainalabedin Navabi, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Utilizing HDL simulation engines for accelerating design and test processes

Zainalabedin Navabi, Najmeh Farajipour, S. Behdad Hosseini, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach

Zainalabedin Navabi, Payman Behnam, Bijan Alizadeh, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A BIST architecture for FPGA look up table testing reduces reconfigurations

Zainalabedin Navabi, Ehsan Atoofian, 2003, 2003 Test Symposium.

Logic Design Concepts

Zainalabedin Navabi, 2005 .

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques

Masahiro Fujita, Zainalabedin Navabi, Bijan Alizadeh, 2012, Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012).

Preface of the 2010 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems. Newswood Limited

Chee Peng Lim, Alie El-Din Mady, Jin Song Dong, 2010 .

Structure specification with a procedural hardware description language

Zainalabedin Navabi, Fredrick J. Hill, M. Masud, 1981, IEEE Transactions on Computers.

A concurrent testing method for NoC switches

Zainalabedin Navabi, Mohammad Hosseinabady, Mahdi Nazm Bojnordi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Hardware Acceleration of Online Error Detection in Many-Core Processors

Zainalabedin Navabi, Arezoo Kamran, 2015, Canadian Journal of Electrical and Computer Engineering.

Path selection and sensor insertion flow for age monitoring in FPGAs

Elaheh Bozorgzadeh, Zainalabedin Navabi, Mohammad Ebrahimi, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An effective VHDL-AMS simulation algorithm with event

Zainalabedin Navabi, Hamid Reza Ghasemi, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Standard IEEE Test Access Methods

Zainalabedin Navabi, 2011 .

Optimistic clock adjustment for preventing Better-than-worst-case violations

Zainalabedin Navabi, Seyedeh Hanieh Hashemi, Reza Namazian, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Compiling an RT level hardware description level into layout of NMOS cells

Zainalabedin Navabi, K Doroudi, 1986 .

An Analytical Model for Reliability Evaluation of NoC Architectures

Zainalabedin Navabi, Mohammad Hosseinabady, Atefe Dalirsani, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

HDL Based Design

Zainalabedin Navabi, 2005 .

A decision-making based approach for fault-handling in multi-agent systems

Majid Nili Ahmadabadi, Zainalabedin Navabi, Maryam S. Mirian, 2002, Proceedings of the 9th International Conference on Neural Information Processing, 2002. ICONIP '02..

Degradable mesh-based on-chip networks using programmable routing tables

Zainalabedin Navabi, Hasan Sohofi, Nima Honarmand, 2007, IEICE Electron. Express.

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits

Zainalabedin Navabi, Bijan Alizadeh, Mahmoud Tabandeh, 2013, IEEE Design & Test.

A low-power high-throughput link splitting router for NoCs

Ali Afzali-Kusha, Zainalabedin Navabi, Mohsen Saneei, 2008 .

Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing

Zainalabedin Navabi, Mohammad Hosseinabady, Shervin Sharifi, 2003, VLSI-SOC.

High-level test generation from VHDL behavioral descriptions

Zainalabedin Navabi, A. M. Gharebaghi, 2000, Proceedings VHDL International Users Forum Fall Workshop.

A UML Based System Level Failure Rate Assessment Technique for SoC Designs

Zainalabedin Navabi, Mohammad Hosseinabady, Mohammad Hossein Neishaburi, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Using context based methods for test data compression

Zainalabedin Navabi, Sara Karamati, 2010, 2010 IEEE International Test Conference.

Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme

Zainalabedin Navabi, Atefesadat Seyedolhosseini, Mahsa Akhsham, 2019, 2019 IEEE European Test Symposium (ETS).

Design for Test by Means of Scan

Zainalabedin Navabi, 2011 .

Languages for Design and Implementation of Hardware

Zainalabedin Navabi, 2006 .

High Level Synthesis of Degradable ASICs Using Virtual Binding

Maghsoud Abbaspour, Zainalabedin Navabi, Hasan Sohofi, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

A Probabilistic and Constraint Based Approach for Low Power Test Generation

Majid Namaki-Shoushtari, Zainalabedin Navabi, Hossein Sabaghian Bidgoli, 2012, 2012 IEEE 21st Asian Test Symposium.

Programmable Routing Tables for Degradable Torus-Based Networks on Chips

Zainalabedin Navabi, Nima Honarmand, Ali Shahabi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Multi-valued logic test access mechanism for test time and power reduction

Zainalabedin Navabi, Amirreza Nekooei, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A novel SAT-based ATPG approach for transition delay faults

Zainalabedin Navabi, Payman Behnam, Vahid Janfaza, 2017, 2017 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Processor Description in APDL for Design Space Exploration of Embedded Processors

Maghsoud Abbaspour, Zainalabedin Navabi, Hassan Sohofi, 2007 .

TLM 2.0 simple sockets synthesis to RTL

Paolo Prinetto, Amirali Ghofrani, Zainalabedin Navabi, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Functional fault simulation of VHDL gate level models

Zainalabedin Navabi, Seyed-Abdollah Aftabjahani, 1997, Proceedings VHDL International Users' Forum. Fall Conference.

An ESL Environment for Modeling Electrical Interconnect Faults

Zainalabedin Navabi, Katayoon Basharkhah, Rezgar Sadeghi, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Universal mitigation of NBTI-induced aging by design randomization

Zainalabedin Navabi, Maksim Jenihhin, Somayeh Sadeghi Kohan, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations

Zainalabedin Navabi, Katayoon Basharkhah, Saba Yousefzadeh, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator

Zainalabedin Navabi, Katayoon Basharkhah, Saba Yousefzadeh, 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing

Zainalabedin Navabi, Saeed Safari, Naghmeh Karimi, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Zainalabedin Navabi, Shahrzad Mirkhani, 2016 .

Sign bit reduction encoding for low power applications

Ali Afzali-Kusha, Zainalabedin Navabi, Mohsen Saneei, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Verilog HDL for Design and Test

Zainalabedin Navabi, Z. Navabi, 2011 .

Deterministic Test Generation Algorithms

Zainalabedin Navabi, 2011 .

DCim++: a C++ library for object oriented hardware design and distributed simulation

Caro Lucas, Zainalabedin Navabi, Hadi Esmaeilzadeh, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A low-power scan-path architecture

Ali Afzali-Kusha, Zainalabedin Navabi, Safar Hatami, 2005, 2005 IEEE International Symposium on Circuits and Systems.

DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation

Zainalabedin Navabi, Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

A Transistor Level Link for VHDL Simulation of VLSI Circuits

Zainalabedin Navabi, Zahra Razavi, 1995, Simul..

An OSCI TLM-2.0 based Platform for Grid Computing Simulation

Zainalabedin Navabi, Mina Zolfy, Ziaddin Daie Koozehkanani, 2010 .

Scan-Based Structure with Reduced Static and Dynamic Power Consumption

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad Hosseinabady, 2006, J. Low Power Electron..

Word-level symbolic simulation in processor verification

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004 .

RT level hardware description with VHDL

Mahsan Rofouei, Zainalabedin Navabi, 2016 .

RT level reliability enhancement by constructing dynamic TMRS

Fabrizio Lombardi, Zainalabedin Navabi, Shahrzad Mirkhani, 2007, GLSVLSI '07.

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

Zainalabedin Navabi, Naghmeh Karimi, Shahrzad Mirkhani, 2006, 2006 15th Asian Test Symposium.

Using integer equations to check PSL properties in RT level design

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

Low cost error tolerant motion estimation for H.264/AVC standard

Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT

Michel Renovell, Sattar Mirzakuchaki, Zainalabedin Navabi, 2007 .

Self-Healing Many-Core Architecture: Analysis and Evaluation

Zainalabedin Navabi, Arezoo Kamran, 2016, VLSI Design.

Enhancing Fault Simulation Performance by Dynamic Fault Clustering

Zainalabedin Navabi, Shahrzad Mirkhani, 2005, 14th Asian Test Symposium (ATS'05).

Assertion-based verification for system-level designs

Zainalabedin Navabi, Hasan Sohofi, Z. Navabi, 2014, Fifteenth International Symposium on Quality Electronic Design.

Designing Library Components

Zainalabedin Navabi, 2005 .

Verilog for Simulation and Synthesis

Zainalabedin Navabi, 2005 .

Homogeneous many-core processor system test distribution and execution mechanism

Zainalabedin Navabi, Arezoo Kamran, 2014, 2014 19th IEEE European Test Symposium (ETS).

High-level design space exploration of locally linear neuro-fuzzy models for embedded systems

Hamid Noori, Zainalabedin Navabi, Mohammadreza Baharani, 2014, Fuzzy Sets Syst..

A novel graceful degradable routing algorithm for 3D on-chip networks

Zainalabedin Navabi, Saeed Safari, Ali Shahabi, 2012, INA-OCMC '12.

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors

Zainalabedin Navabi, Fatemeh Refan, Bijan Alizadeh, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Stall Power Reduction in Pipelined Architecture Processors

Ali Afzali-Kusha, Amir-Mohammad Rahmani, Zainalabedin Navabi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

A Low Power BIST Architecture for FPGA Look-Up Table Testing

Zainalabedin Navabi, Ehsan Atoofian, 2003, VLSI-SOC.

Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits

Zainalabedin Navabi, 1991 .

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies

Behzad Ebrahimi, Ali Afzali-Kusha, Massoud Pedram, 2015, Integr..

A new protocol stack model for network on chip

Ali Afzali-Kusha, Zainalabedin Navabi, Mohsen Nickray, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

An Exhaustive Test Strategy Based on Flooding Routing for NoC Switch Testing

Mahmood Fathy, Armin Alaghi, Zainalabedin Navabi, 2007 .

Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems

Zainalabedin Navabi, Rasool Sharifi, Z. Navabi, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Behavioral VHDL transistor slope models

Zainalabedin Navabi, J. Dube, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Soft Error Analysis on Communication Channels in On-Chip Communication Networks

Zainalabedin Navabi, Saeed Safari, Mohammadreza Najafi, 2012, 2012 15th Euromicro Conference on Digital System Design.

A partitioning approach to improve reconfigurable neuron-inspired online BIST

Zainalabedin Navabi, Hasan Sohofi, Ali Shahabi, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

The Scalable and Reconfigurable DFT for Embedded A/MS Cores

Michel Renovell, Sattar Mirzakuchaki, Zainalabedin Navabi, 2006 .

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs

Mohammad Ebrahimi, Zainalabedin Navabi, Nader Bagherzadeh, 2017, IEEE Transactions on Computers.

Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture

Zainalabedin Navabi, Somayeh Sadeghi Kohan, Ramin Rezaeizadeh Rookerd, 2018, ACM Great Lakes Symposium on VLSI.

Utilizing various ADL facets for instruction level CPU test

Maghsoud Abbaspour, Zainalabedin Navabi, Zohreh Karimi, 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs

Masoud Daneshtalab, Zainalabedin Navabi, Caro Lucas, 2008, 2008 Design, Automation and Test in Europe.

AHPL COMPILER/SIMULATOR SYSTEM.

Zainalabedin Navabi, Frederick J. Hill, Robert E. Swanson, 1800 .

Memory Testing by Means of Memory BIST

Zainalabedin Navabi, Z. Navabi, 2011 .

Ant colony based routing architecture for minimizing hot spots in NOCs

Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi, 2006, SBCCI '06.

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Mahmood Fathy, Zainalabedin Navabi, Mohammadreza Najafi, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

Using data compression in automatic test equipment for system-on-chip testing

Fabrizio Lombardi, Waleed Meleis, Zainalabedin Navabi, 2004, IEEE Transactions on Instrumentation and Measurement.

VHDL-AMS hardware description language

Zainalabedin Navabi, Naghmeh Karimi, 2016 .

Report on VHDL methods workshop

Zainalabedin Navabi, 1990, SIGD.

TED+: a data structure for microprocessor verification

Zainalabedin Navabi, Mohammad Hosseinabady, Mehran Massoumi, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Tools for Design and Prototyping

Zainalabedin Navabi, 2005 .

An improved scheme for pre-computed patterns in core-based SoC architecture

Mahmood Fathy, Zainalabedin Navabi, Paniz Foroutan, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

A reconfigurable online BIST for combinational hardware using digital neural networks

Zainalabedin Navabi, Hasan Sohofi, Ali Shahabi, 2010, 2010 15th IEEE European Test Symposium.

SCOAP-based Directed Random Test Generation for Combinational Circuits

Zainalabedin Navabi, Maryam Rajabalipanah, Seyyede Maryam Ghasemy, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Architecture design and technical methodology for bus testing

M. H. Haghbayan, Zainalabedin Navabi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors

Zainalabedin Navabi, Fatemeh Refan, Bijan Alizadeh, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library

Zainalabedin Navabi, Shahrzad Mirkhani, Parisa Razaghi, 2007, FDL.

Low-power and low-latency cluster topology for local traffic NoCs

Ali Afzali-Kusha, Zainalabedin Navabi, Mohsen Saneei, 2006, 2006 IEEE International Symposium on Circuits and Systems.

VHDL: Analysis and Modeling of Digital Systems

Zainalabedin Navabi, Z. Navabi, 1992 .

DIGITIZING FOR COMPUTER-AIDED FINITE ELEMENT MODEL GENERATION

Zainalabedin Navabi, H. A. Kamel, 1979 .

An efficient BIST method for testing of embedded SRAMs

Zainalabedin Navabi, Sied Mehdi Fakhraie, Mohammad H. Tehranipour, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model

Armin Alaghi, Zainalabedin Navabi, Mahshid Sedghi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Basics of Test and Role of HDLs

Zainalabedin Navabi, Z. Navabi, 2011 .

Effective RT-level software-based self-testing of embedded processor cores

Zainalabedin Navabi, Parisa Kabiri, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Dynamic Power Reduction of Stalls in Pipelined Architecture Processors

Ali Afzali-Kusha, Amir-Mohammad Rahmani, Zainalabedin Navabi, 2011 .

Modeling strategy for post layout verification

Zainalabedin Navabi, J. Dube, A. Huang, 1990, Third Annual IEEE Proceedings on ASIC Seminar and Exhibit.

AIRE/CE: a revision towards CAD tool integration

Zainalabedin Navabi, Amir Masoud Gharehbaghi, M. H. Reshadi, 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

Near optimal machine learning based random test generation

Majid Nili Ahmadabadi, Nastaran Nemati, Zainalabedin Navabi, 2010, 2010 East-West Design & Test Symposium (EWDTS).

ByZFAD: a low switching activity architecture for shift-and-add multipliers

Ali Afzali-Kusha, Zainalabedin Navabi, Mohammad D. Mottaghi, 2006, SBCCI '06.

Templates for synthesis from VHDL

Zainalabedin Navabi, J. Spillane, 1990, Third Annual IEEE Proceedings on ASIC Seminar and Exhibit.

A VHDL based test environment including models for equivalence fault collapsing

Zainalabedin Navabi, M. Shadfar, 1994, Proceedings of VHDL International Users Forum.

"Plug & Test" at System Level via Testable TLM Primitives

Paolo Prinetto, Stefano Di Carlo, Zainalabedin Navabi, 2008, 2008 IEEE International Test Conference.

Tutorial on use of VHDL for description of digital systems

Zainalabedin Navabi, S. Day, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

M. H. Haghbayan, Zainalabedin Navabi, Fatemeh Javaheri, 2010, 2010 19th IEEE Asian Test Symposium.

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links

Zainalabedin Navabi, Katayoon Basharkhah, Rezgar Sadeghi, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Embedded Core Design with FPGAs

Zainalabedin Navabi, Z. Navabi, 2006 .

VLSI DESIGN AUTOMATION USING A HARDWARE PROGRAMMING LANGUAGE

Zainalabedin Navabi, 1981 .

Hardware Compilation from an RTL to a Storage Logic Array Target

Duan-Ping Chen, Zainalabedin Navabi, C. H. Chiang, 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Role Reconfiguration Based on Decision-Making for Fault-Recovering in Multi- Agent Systems

Majid Nili Ahmadabadi, Zainalabedin Navabi, Maryam S. Mirian, 2002 .

EDXY - A low cost congestion-aware routing algorithm for network-on-chips

Masoud Daneshtalab, Ali Afzali-Kusha, Amir-Mohammad Rahmani, 2010, J. Syst. Archit..

Instruction level test methodology for CPU core software-based self-testing

Zainalabedin Navabi, Hadi Esmaeilzadeh, Saeed Shamshiri, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

A TLM2.0 assertion library with centralized monitoring approach

Amirali Ghofrani, Zainalabedin Navabi, Sheis Abolma'ali, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Configurable Systolic Matrix Multiplication

Zainalabedin Navabi, Parastoo Kamranfar, Ali Shahabi, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

The impact of hardware description languages on the education of hardware design

Zainalabedin Navabi, 1989, Proceedings., Eighth University/Government/Industry Microelectronics Symposium.

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model

Pasi Liljeberg, Amir-Mohammad Rahmani, M. H. Haghbayan, 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester

Zainalabedin Navabi, Katayoon Basharkhah, Nooshin Nosrati, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Integrating an Interconnect BIST with Crosstalk Avoidance Hardware

Zainalabedin Navabi, Mahsa Akhsham, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

AFTAB: A RISC-V Implementation with Configurable Gateways for Security

Paolo Prinetto, Zainalabedin Navabi, Gianluca Roascio, 2021, 2021 IEEE East-West Design & Test Symposium (EWDTS).

Online Testing of a Row-Stationary Convolution Accelerator

Zainalabedin Navabi, Katayoon Basharkhah, Mohammad Rasoul Roshanshah, 2021, 2021 IEEE European Test Symposium (ETS).

n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator

Zainalabedin Navabi, Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Intermediate Format Standardization : Ambiguities , Deficiencies , Portability issues , Documentation and Improvements

Zainalabedin Navabi, Amir Masoud Gharehbaghi, Mohammad Hossein Reshadi, 2003 .

Using VHDL Neural Network Models for Automatic Test Generation

Zainalabedin Navabi, Armita Peymandoust, Morteza Fayyazi, 1999 .

An Efficient Online BIST Architecture for NoCs

Zainalabedin Navabi, Mohammad Hosseinabady, Mahdi Nazm Bojnordi, 2006 .