Yung-Ching Hsieh

An efficient layout style for 2-metal CMOS leaf cells and their automatic generation

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1991, 28th ACM/IEEE Design Automation Conference.

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An optimal transistor-chaining algorithm for CMOS cell layout

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

LiB: a CMOS cell compiler

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache

Wei Wu, Zhe Wang, Ding-Ming Kwai, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

LiB: a cell layout generator

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1991, DAC '90.