David H. Albonesi

发表

Scheduling algorithms for unpredictably heterogeneous CMP architectures

Jonathan A. Winter, David H. Albonesi, 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

Margaret Martonosi, David I. August, David H. Albonesi, 2009, MICRO 2009.

DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks

David H. Albonesi, Rajit Manohar, Saber Moradi, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

The Energy Impact of Aggressive Loop Fusion

Chen Ding, Michael L. Scott, David H. Albonesi, 2004, IEEE PACT.

Tradeoffs in power-efficient issue queue design

Pradip Bose, David H. Albonesi, Alper Buyuktosunoglu, 2002, ISLPED '02.

The Inherent Energy Efficiency of Complexity-Adaptive Processors

David H. Albonesi, D. Albonesi, 1998 .

Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects

Eby G. Friedman, Philippe M. Fauchet, David H. Albonesi, 2007 .

Selective cache ways: on-demand cache resource allocation

David H. Albonesi, D. Albonesi, 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Michael L. Scott, David H. Albonesi, Grigorios Magklis, 2003, ISCA '03.

Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling

Zhiru Zhang, David H. Albonesi, Abhinandan Majumdar, 2016, 2016 ACM/IEEE 7th International Conference on Cyber-Physical Systems (ICCPS).

Improving the memory bandwidth of highly-integrated, wide-issue, microprocessor-based systems

Israel Koren, David H. Albonesi, 1997, Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques.

A phase adaptive cache hierarchy for SMT processors

José Ignacio Hidalgo, David H. Albonesi, Oscar Garnica, 2011, Microprocess. Microsystems.

Runtime Reconfiguration Techniques for Efficient General-Purpose Computation

David H. Albonesi, Bingxiong Xu, D. Albonesi, 2000, IEEE Des. Test Comput..

On-Chip Optical Technology in Future Bus-Based Multicore Designs

Alyssa B. Apsel, José F. Martínez, David H. Albonesi, 2007, IEEE Micro.

Changes Ahead

David H. Albonesi, 2008, IEEE Micro.

STATS: A framework for microprocessor and system-level design space exploration

Israel Koren, David H. Albonesi, 1999, J. Syst. Archit..

A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity

David H. Albonesi, Alper Buyuktosunoglu, YongKang Zhu, 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors

David H. Albonesi, Mark J. Cianchetti, D. Albonesi, 2011, JETC.

A circuit level implementation of an adaptive issue queue for power-aware microprocessors

David M. Brooks, Pradip Bose, David H. Albonesi, 2001, GLSVLSI '01.

QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education

David H. Albonesi, Edwin J. Tan, Gregory J. Briggs, 2005, WCAE '05.

The energy impact of aggressive loop fusion

Chen Ding, Michael L. Scott, David H. Albonesi, 2004, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004..

Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor

David H. Albonesi, Grigorios Magklis, Michael L. Scott, 2003 .

Dynamic IPC/clock rate optimization

David H. Albonesi, 1998, ISCA.

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores

Christina Delimitrou, Christine A. Shoemaker, David H. Albonesi, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Editor in Chief's Message: Truly "hot" chips - Do we still care?

David H. Albonesi, 2007, IEEE Micro.

Dynamic data dependence tracking and its applications

David H. Albonesi, Lei Chen, 2004 .

Exploiting coarse-grain verification parallelism for power-efficient fault tolerance

Michael C. Huang, David H. Albonesi, M. Wasiur Rashid, 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

Energy efficient co-adaptive instruction fetch and issue

Tejas Karkhanis, Pradip Bose, David H. Albonesi, 2003, ISCA '03.

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2000, MICRO 33.

Partitioning Multi-Threaded Processors with a Large Number of Threads

Sandhya Dwarkadas, David H. Albonesi, Ali El-Moursy, 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

Dynamically allocating processor resources between nearby and distant ILP

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

Mitigating inductive noise in SMT processors

David H. Albonesi, W. El-Essawy, 2004 .

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor

James E. Smith, Michael Gschwind, Tejas Karkhanis, 2002, PACS.

Guest Editors' Introduction: Power and Complexity Aware Design

Pradip Bose, Diana Marculescu, David H. Albonesi, 2003, IEEE Micro.

A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques

Israel Koren, David H. Albonesi, D. Albonesi, 1996, International Journal of Parallel Programming.

From the Editor in Chief: Welcome A-Board

David H. Albonesi, 2009, IEEE Micro.

Multiple clock domain microarchitecture design and analysis

David H. Albonesi, Greg Semeraro, 2003 .

Managing static leakage energy in microprocessor functional units

Eby G. Friedman, Sandhya Dwarkadas, Volkan Kursun, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Localized microarchitecture-level voltage management

David H. Albonesi, YongKang Zhu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors

David H. Albonesi, Matthew A. Watkins, 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA

Margaret Martonosi, David I. August, David H. Albonesi, 2009, MICRO.

Managing static leakage energy in microprocessor functional units

Eby G. Friedman, Sandhya Dwarkadas, Volkan Kursun, 2002, MICRO.

On-chip optical interconnect for reduced delay uncertainty

Hui Chen, Guoqing Chen, Eby G. Friedman, 2007, Nano-Net.

Dynamically allocating processor resources between nearby and distant ILP

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2001, ISCA 2001.

A Circuit Level Implementation of an Adaptive Issue for Power-Aware Microprocessors Queue

Pradip Bose, David H. Albonesi, David Brooks, 2001 .

Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors

David H. Albonesi, Oscar Garnica, Juan Lanchares, 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures

David H. Albonesi, D. Albonesi, 1999, VLSI.

Shared reconfigurable architectures for CMPS

David H. Albonesi, Matthew A. Watkins, Mark J. Cianchetti, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Dynamic data dependence tracking and its application to branch prediction

Lei Chen, David H. Albonesi, Steven G. Dropsho, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

Future Directions in Computer Architecture Research

David H. Albonesi, 2010, IEEE Micro.

ReMAP: A Reconfigurable Architecture for Chip Multiprocessors

David H. Albonesi, Matthew A. Watkins, 2011, IEEE Micro.

Predictions of CMOS compatible on-chip optical interconnect

Hui Chen, Guoqing Chen, Eby G. Friedman, 2005, International Workshop on System-Level Interconnect Prediction.

Microarchitectural Trade-Offs in the Design of a Scalable Clustered Microprocessor

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2002 .

Integrating adaptive on-chip storage structures for reduced dynamic power

Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

Methodology for the analysis of dynamic application parallelism and its application to reconfigurable computing

David H. Albonesi, Bingxiong Xu, D. Albonesi, 1999, Optics East.

Phastlane: a rapid transit optical routing network

David H. Albonesi, Mark J. Cianchetti, Joseph C. Kerekes, 2009, ISCA '09.

Reconfigurable architectures for chip multiprocessors

David H. Albonesi, Matthew A. Watkins, D. Albonesi, 2010 .

Dynamic GPGPU Power Management Using Adaptive Model Predictive Control

Indrani Paul, Wei Huang, David H. Albonesi, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Mixing It Up

David H. Albonesi, D. Albonesi, 2007, IEEE Micro.

Reducing the complexity of the register file in dynamic superscalar processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

Standing on Solid Ground

David H. Albonesi, 2007, IEEE Micro.

Moving Forward

David H. Albonesi, 2010, IEEE Micro.

Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture

David H. Albonesi, Steven Dropsho, Lei Chen, 2004 .

On-chip optical interconnect roadmap: challenges and critical directions

Eby G. Friedman, Jidong Zhang, Philippe M. Fauchet, 2005 .

Dynamically managing the communication-parallelism trade-off in future clustered processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2003, ISCA '03.

An Adaptive Issue Queue for Reduced Power at High Performance

David M. Brooks, Pradip Bose, David H. Albonesi, 2000, PACS.

Highly efficient multithreaded architecture

David H. Albonesi, Ali A. El-Moursy, 2005 .

Front-end policies for improved issue efficiency in SMT processors

David H. Albonesi, Ali El-Moursy, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

Architecture and technology tradeoffs in the design of next-generation multiprocessor servers

Israel Koren, David H. Albonesi, 1995, Proceedings.Seventh IEEE Symposium on Parallel and Distributed Processing.

A microarchitectural-level step-power analysis tool

Balaram Sinharoy, David H. Albonesi, Wael El-Essawy, 2002, ISLPED '02.

Dynamic Memory Hierarchy Performance Optimization

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2000 .

Hardware and software optimizations for multiple clock domain microprocessors

David H. Albonesi, YongKang Zhu, 2005 .

Flicker: a dynamically adaptive architecture for power limited multicore systems

Christine A. Shoemaker, David H. Albonesi, Adam M. Izraelevitz, 2013, ISCA.

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques Held 24-26 August 1994 in Montreal, Canada

Mitsuhisa Sato, David H. Albonesi, Trung N. Nguyen, 1994 .

Predictions of CMOS compatible on-chip optical interconnect

Hui Chen, Guoqing Chen, Eby G. Friedman, 2005, SLIP '05.

A High Performance Two-Level Register File Organization

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2001 .

Energy-aware meeting scheduling algorithms for smart buildings

Pradip Bose, David H. Albonesi, Abhinandan Majumdar, 2012, BuildSys '12.

Reducing the complexity of the register file in dynamic superscalar processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2001, MICRO.

2015 International Symposium on Computer Architecture Influential Paper Award

David H. Albonesi, 2016, IEEE Micro.

Processor Performance Enhancement Using Self-Adaptive Clock Frequency

Jose Renau, Sung Woo Chung, David H. Albonesi, 2010 .

Tradeoffs in the Design of Single Chip Multiprocessors

Israel Koren, David H. Albonesi, D. Albonesi, 1994, IFIP PACT.

Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences

David H. Albonesi, 2004, IEEE Micro.

Power-efficient error tolerance in chip multiprocessors

Michael C. Huang, David H. Albonesi, M. Wasiur Rashid, 2005, IEEE Micro.

Productive and Healthy Debate

David H. Albonesi, 2007, IEEE Micro.

An analytical model of high performance superscalar-based multiprocessors

Israel Koren, David H. Albonesi, D. Albonesi, 1995, PACT.

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Sandhya Dwarkadas, David H. Albonesi, Grigorios Magklis, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015

David H. Albonesi, Debbie Marr, 2015, ISCA.

Hiding synchronization delays in a GALS processor microarchitecture

Michael L. Scott, Sandhya Dwarkadas, David H. Albonesi, 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications

Wanli Liu, Lloyd Palum, David H. Albonesi, 2004, J. Circuits Syst. Comput..

Compatible phase co-scheduling on a CMP of multi-threaded processors

Sandhya Dwarkadas, David H. Albonesi, Ali El-Moursy, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

David H. Albonesi, Oscar Garnica, Juan Lanchares, 2007, HiPEAC.

Electrical and optical on-chip interconnects in scaled microprocessors

Hui Chen, Guoqing Chen, Eby G. Friedman, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Michael L. Scott, Sandhya Dwarkadas, David H. Albonesi, 2002, MICRO.

A Performance On-Demand Approach to Power-Efficient Computing

Eby G. Friedman, Sandhya Dwarkadas, David H. Albonesi, 2004 .

An old-est-first selection logic implementation for non-compacting issue queues

David H. Albonesi, Alper Buyuktosunoglu, Ali A. El-Moursy, 2002 .

More Hot Stuff

David H. Albonesi, 2007, IEEE Micro.

A dynamic reconfigurable clock generator

Eby G. Friedman, David H. Albonesi, R. M. Secareanu, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

A Dynamically Tunable Memory Hierarchy

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, 2003, IEEE Trans. Computers.

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

Michael L. Scott, David H. Albonesi, Grigorios Magklis, 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture

David H. Albonesi, Matthew A. Watkins, D. Albonesi, 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

Dynamically Tuning Processor Resources with Adaptive Processing

Michael C. Huang, Pradip Bose, Eby G. Friedman, 2003, Computer.

Synergistic Temperature and Energy Management in GALS Processor Architectures

David H. Albonesi, YongKang Zhu, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Christine A. Shoemaker, Jonathan A. Winter, David H. Albonesi, 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

Power-efficient issue queue design

Pradip Bose, David H. Albonesi, David Brooks, 2002 .

Addressing thermal nonuniformity in SMT workloads

Jonathan A. Winter, David H. Albonesi, D. Albonesi, 2008, TACO.

Energy-comfort optimization using discomfort history and probabilistic occupancy prediction

David H. Albonesi, Brandon Hencey, Abhinandan Majumdar, 2014, International Green Computing Conference.

Toolbox for exploration of energy-efficient event processors for human-computer interaction

David H. Albonesi, Jaeyeon Kihm, Rajit Manohar, 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Alyssa B. Apsel, José F. Martínez, David H. Albonesi, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Cache Design Options for a Clustered Multithreaded Architecture

Sandhya Dwarkadas, David H. Albonesi, Rajeev Garg, 2005 .