Yuran Qiao

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA

Zelong Wang, Junzhong Shen, You Huang, 2018, FPGA.

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA

Junzhong Shen, Yuran Qiao, Mei Wen, 2017, NPC.

Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA

Junzhong Shen, Yuran Qiao, Mei Wen, 2015, ICA3PP.

MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA

Junzhong Shen, You Huang, Yuran Qiao, 2018, IEICE Electron. Express.

FPGA‐accelerated deep convolutional neural networks for high throughput and energy efficiency

Junzhong Shen, Yuran Qiao, Mei Wen, 2017, Concurr. Comput. Pract. Exp..

ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit

Nan Wu, Yuran Qiao, Mei Wen, 2013, APPT.

Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs

Dong Chen, Nan Wu, Xing Cai, 2014, Euro-Par.

A Workload Sensitive Dynamic Scaling Matrix Multiplier Structure

Junzhong Shen, Yuran Qiao, Qianming Yang, 2016, 2016 8th International Conference on Computational Intelligence and Communication Networks (CICN).

Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs

Junzhong Shen, You Huang, Yuran Qiao, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).