Sylvain Clerc

发表

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Robin Wilson, Arnaud Virazel, Alberto Bosio, 2015, Sixteenth International Symposium on Quality Electronic Design.

Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs

Olivier Billoint, Edith Beigné, Bastien Giraud, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm

Bertrand Pelloux-Prayer, Sylvain Clerc, Fady Abouzeid, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Kaya Can Akyel, Sylvain Clerc, Fady Abouzeid, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

Sylvain Clerc, Philippe Roche, Gilles Gasiot, 2013, IEEE Transactions on Nuclear Science.

Bistable circuit for e.g. hybrid latch flip-flop, has delay chain defining temporal window around pulse front of clock signal and comprising transistors for temporally adjusting duration of window during discharging of intermediate node

Sylvain Clerc, 2006 .

Design methodology with body bias: From circuit to engineering

Philippe Flatresse, Sylvain Clerc, Vincent Huard, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Gilles Sicard, Sylvain Clerc, Fady Abouzeid, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications

Gilles Sicard, Marc Renaudin, Sylvain Clerc, 2009, ISLPED.

A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition

Sylvain Clerc, Guillaume Moritz, Fabrice Guellec, 2020, 2020 IEEE Symposium on VLSI Circuits.

Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI

Dennis Sylvester, Bertrand Pelloux-Prayer, Sylvain Clerc, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking

Olivier Billoint, Christian Bernard, Fabien Clermidy, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

65 nm fault tolerant latch architecture based on transient propagation blocking

Sylvain Clerc, Philippe Roche, Gilles Gasiot, 2014, 2014 IEEE International Reliability Physics Symposium.

Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology

Sylvain Clerc, Ricardo Gomez Gomez, Edwige Bano, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Digital Design Implementation Flow and Verification Methodology

Sylvain Clerc, Damien Riquet, Sebastien Marchal, 2020 .

30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation

Sylvain Clerc, Fady Abouzeid, Jean-Marc Daveau, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

30% static power improvement on ARM Cortex®-A53 using static Biasing-Anticipation

Sylvain Clerc, Fady Abouzeid, Jean-Marc Daveau, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Body-Bias for Digital Designs

Sylvain Clerc, Ricardo Gomez Gomez, 2020 .

Charge Collection Physical Modeling for Soft Error Rate Computational Simulation in Digital Circuits

Sylvain Clerc, Daniela Munteanu, Gilles Gasiot, 2016 .

Method for managing the operation of a redundant circuit and device combines majority voting

Sylvain Clerc, Jean-Marc Daveau, Philippe Roche, 2014 .

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

Rajesh Kumar, Sylvain Clerc, Fady Abouzeid, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Olivier Billoint, Christian Bernard, Robin Wilson, 2015, IEEE Journal of Solid-State Circuits.

Timing-Based Closed Loop Compensation

Sylvain Clerc, Ricardo Gomez Gomez, 2020 .

A method of managing the operation of a redundant majority decision circuit and associated apparatus

Sylvain Clerc, Jean-Marc Daveau, Philippe Roche, 2015 .

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Sylvain Clerc, Olivier Callen, Brice Lhomme, 2010, 2010 Proceedings of ESSCIRC.

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

Bertrand Pelloux-Prayer, Sylvain Clerc, Fady Abouzeid, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A 28nm FD-SOI standard cell 0.6–1.2V open-loop frequency multiplier for low power SoC clocking

Sylvain Clerc, Philippe Roche, Pierre Schamberger, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Detailed SET Measurement and Characterization of a 65 nm Bulk Technology

Adrian Evans, Dan Alexandrescu, Sylvain Clerc, 2017, IEEE Transactions on Nuclear Science.

Body-Bias Calibration Based Temperature Sensor

Andreia Cathelin, Sylvain Clerc, Fady Abouzeid, 2020 .

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits

Sylvain Clerc, Philippe Roche, Jean-Luc Autran, 2014, Microelectron. Reliab..

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC

Borivoje Nikolic, Sylvain Clerc, Philippe Roche, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2012, 2012 IEEE International Conference on IC Design & Technology.

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

David Bol, Julien De Vos, Dennis Sylvester, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI

Robin Wilson, Kaya Can Akyel, Sylvain Clerc, 2014, IEEE Journal of Solid-State Circuits.

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test

Lirida A. B. Naviner, Sylvain Clerc, Fady Abouzeid, 2015, 2015 IEEE International Reliability Physics Symposium.

SRAM memory cell random ten transistors

Sylvain Clerc, Fady Abouzeid, 2010 .

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Gilles Sicard, Marc Renaudin, Sylvain Clerc, 2011, TODE.

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors

Sylvain Clerc, Fady Abouzeid, Jean-Marc Daveau, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC)

Patrick Reynaert, Sylvain Clerc, Lucien J. Breems, 2020, IEEE J. Solid State Circuits.

Open Loop Compensation

Sylvain Clerc, Ricardo Gomez Gomez, 2020 .

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies

Sylvain Clerc, Kedar Janardan Dhori, Christian Dutto, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A commercial 65nm CMOS technology for space applications: Heavy ion, proton and gamma test results and modeling

Sylvain Clerc, Jean-Marc Daveau, Philippe Roche, 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

Sylvain Clerc, Jean-Marc Daveau, Philippe Roche, 2010, IEEE Transactions on Nuclear Science.

Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2013, IEEE Transactions on Nuclear Science.

Investigating the single-event-transient sensitivity of 65 nm clock trees with heavy ion irradiation and Monte-Carlo simulation

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).