Lorenzo Ciampolini

发表

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Robin Wilson, Arnaud Virazel, Alberto Bosio, 2015, Sixteenth International Symposium on Quality Electronic Design.

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications

R. Ranica, Lorenzo Ciampolini, Fabien Giner, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A predictive analytical modelof3DMIM capacitors forRC IC

Lorenzo Ciampolini, Daniel Gloria, Sebastien Cremer, 2007 .

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Kaya Can Akyel, Sylvain Clerc, Fady Abouzeid, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs

Lorenzo Ciampolini, David Turgis, Gérard Ghibaudo, 2016, 2016 IEEE 25th North Atlantic Test Workshop (NATW).

Electronic component integrating an array of cells tcam

Lorenzo Ciampolini, David Turgis, Olivier Menut, 2013 .

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI

Andreia Cathelin, Oskar Andersson, Joachim Neves Rodrigues, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI

Kaya Can Akyel, Olivier Thomas, Lorenzo Ciampolini, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells

Lorenzo Ciampolini, David Turgis, Jean-Paul Morin, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications

Bastien Giraud, Jean-Philippe Noel, Edith Beigne, 2018, IEEE Solid-State Circuits Letters.

High-yield design of high-density SRAM for low-voltage and low-leakage operations

Prashant Pandey, Lorenzo Ciampolini, Hitesh Chawla, 2017, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell

Bruno Allard, Lorenzo Ciampolini, David Turgis, 2012, 2012 International SoC Design Conference (ISOCC).

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI

Robin Wilson, Kaya Can Akyel, Sylvain Clerc, 2014, IEEE Journal of Solid-State Circuits.

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI

Andreia Cathelin, Oskar Andersson, Joachim Neves Rodrigues, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

RAPIDO Testing of Assisted Write and Read operations for SRAMs

Lorenzo Ciampolini, David Turgis, Olivier Callen, 2016 .

Storage Class Memory with Computing Row Buffer: A Design Space Exploration

Bastien Giraud, Jean-Philippe Noel, Lorenzo Ciampolini, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs

Bastien Giraud, B. Blampey, Lorenzo Ciampolini, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

Scanning capacitance microscope imaging and modelling

Lorenzo Ciampolini, 2001 .