Geeng-Lih Lin

Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

Ming-Dou Ker, Sheng-Fu Hsu, Yeh-Ning Jou, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

Ming-Dou Ker, Yeh-Ning Jou, Geeng-Lih Lin, 2015, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC).

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection design with latchup-free immunity in 120V SOI process

Ming-Dou Ker, Yeh-Ning Jou, Geeng-Lih Lin, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Ming-Dou Ker, Jia-Rong Yeh, Yeh-Ning Jou, 2015, 2015 European Conference on Circuit Theory and Design (ECCTD).

The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs

Bing-Yue Tsui, Geeng-Lih Lin, C.T. Huang, 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.