K. Cheng

发表

Advanced flexible CMOS integrated circuits on plastic enabled by controlled spalling technology

M. Gaynes, A. Khakifirooz, D. Shahrjerdi, 2012, 2012 International Electron Devices Meeting.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

N. Loubet, P. Kulkarni, H. Bu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Extremely thin SOI (ETSOI) technology: Past, present, and future

P. Kulkarni, H. Bu, A. Khakifirooz, 2010, 2010 IEEE International SOI Conference (SOI).

Yield Learning Methodologies and Failure Isolation in Ring Oscillator Circuit for CMOS Technology Research

K. Cheng, Victor Chan, T. M. Levin, 2019, IEEE Transactions on Semiconductor Manufacturing.

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

O. Rozeau, O. Faynot, G. Ghibaudo, 2014, 2014 IEEE International Electron Devices Meeting.

Device design considerations for next generation CMOS technology: Planar FDSOI and FinFET (Invited)

M. Vinet, A. Khakifirooz, K. Cheng, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Failure Isolation in Ring Oscillator Circuit and Defect Detection in CMOS Technology Research

K. Cheng, J. Strane, T. Levin, 2019, 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Air spacer for 10nm FinFET CMOS and beyond

M. Wang, T. Yamashita, H. Bu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

P. Oldiges, B. Haran, H. Bu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A new technique to quantify deuterium passivation of interface traps in MOS devices

K. Cheng, K. Hess, J. Lyding, 2001, IEEE Electron Device Letters.

Novel techniques for scaling deep trench DRAM capacitor technology to 0.11 /spl mu/m and beyond

R. Jammy, D.-G. Park, K. Cheng, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

10nm FINFET technology for low power and high performance applications

D. Chanemougame, P. Oldiges, B. Haran, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.

Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates

K. Cheng, D. Caimi, L. Czornomaz, 2013, 2013 IEEE International Electron Devices Meeting.

A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond

W. Mueller, K. Varn, R. Jammy, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).