Steve Dai

发表

Design, simulation, and evaluation of imaging oximeters

Ye Tian, Joyce E. Farrell, Steve Dai, 2013, Electronic Imaging.

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, IEEE Solid-State Circuits Letters.

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Area-efficient pipelining for FPGA-targeted high-level synthesis

Zhiru Zhang, Ritchie Zhao, Mingxing Tan, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

Shreesha Srinath, Christopher Batten, Zhiru Zhang, 2017, FPGA.

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Zhiru Zhang, Udit Gupta, Mingxing Tan, 2015, FPGA.

Design and Evaluation of Identifiable Key-Click Signals for Mobile Devices

Hong Z. Tan, Jaeyoung Park, Steve Dai, 2011, IEEE Transactions on Haptics.

High-Level Synthesis with Timing-Sensitive Information Flow Enforcement

Zhiru Zhang, G. Edward Suh, Zhenghong Jiang, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Accelerating Chip Design With Machine Learning

William J. Dally, Yanqing Zhang, Brucek Khailany, 2020, IEEE Micro.

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, 2019 Symposium on VLSI Circuits.

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Christopher Torng, Christopher Batten, Ronald G. Dreslinski, 2018, IEEE Micro.

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis

Zhiru Zhang, Rajit Manohar, Steve Dai, 2017, FPGA.

Enabling adaptive loop pipelining in high-level synthesis

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning

Evangeline F. Y. Young, Yuan Zhou, Zhiru Zhang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Flushing-enabled loop pipelining for high-level synthesis

Zhiru Zhang, Kecheng Hao, Mingxing Tan, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

Yuan Zhou, Zhiru Zhang, Wenping Wang, 2018, FPGA.

High-level Synthesis for Low-power Design

Zhiru Zhang, Deming Chen, Keith A. Campbell, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

Multithreaded pipeline synthesis for data-parallel kernels

Zhiru Zhang, Bin Liu, Mingxing Tan, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Redundant coding of simulated tactile key clicks with audio signals

Hong Z. Tan, Jaeyoung Park, Steve Dai, 2010, 2010 IEEE Haptics Symposium.

Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning

Zhiru Zhang, Steve Dai, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation

Zhiru Zhang, Gai Liu, Steve Dai, 2018, FPGA.

MAGNet: A Modular Accelerator Generator for Neural Networks

William J. Dally, Brucek Khailany, Jason Clemons, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference pdf

William J. Dally, Brucek Khailany, Brian Zimmer, 2021, MLSys.

Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update pdf

Anima Anandkumar, Brucek Khailany, Ming-Yu Liu, 2021, ArXiv.

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs

Pat Hanrahan, Steve Dai, Dillon Huff, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Anand Raghunathan, Brucek Khailany, Jacob R. Stevens, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking pdf

Brucek Khailany, Nathaniel Pinckney, Haoxing Ren, 2021, ArXiv.

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs

Pat Hanrahan, Steve Dai, Dillon Huff, 2021, FPGA.

Rosetta : A Realistic Benchmark Suite for Software Programmable FPGAs

Udit Gupta, Steve Dai, Zhiru Zhang, 2015 .