D. Heidel

A low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

Pong-Fei Lu, L. Sigal, N. Cao, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Technologies to further reduce soft error susceptibility in SOI

P. Oldiges, L. Wissel, D. Heidel, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Minimizing inductive noise in system-on-a-chip with multiple power gating structures

Suhwan Kim, D.R. Knebel, D. Heidel, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

Stacked devices for SEU immune design

P. Oldiges, L. Wissel, D. Heidel, 2010, 2010 IEEE International SOI Conference (SOI).

Soft error rate scaling for emerging SOI technology options

K. Bernstein, H.-S.P. Wong, P. Oldiges, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).