B.B. Bhattacharya

Accelerated Functional Testing of Digital Microfluidic Biochips

H. Rahaman, K. Chakrabarty, D. Mitra, 2008, 2008 17th Asian Test Symposium.

Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers

A. Pal, B.B. Bhattacharya, G. Paul, 2006, 2006 International Conference on Electrical and Computer Engineering.

Digital Microfluidic Biochips: Design and Testing

B.B. Bhattacharya, 2008, 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems.

Geometric bipartitioning problem and its applications to VLSI

B.B. Bhattacharya, P.S. Dasgupta, A.K. Sen, 1996, Proceedings of 9th International Conference on VLSI Design.

Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells

A. Pal, B.B. Bhattacharya, G. Paul, 2008, 2008 3rd International Design and Test Workshop.

Routing of L-shaped channels, switchboxes and staircases in Manhattan-diagonal model

B.B. Bhattacharya, S. Sur-Kolay, S. Das, 1998, Proceedings Eleventh International Conference on VLSI Design.

Physical design trends and layout-based fault modeling

P. Dasgupta, B.B. Bhattacharya, S.T. Zachariah, 2004, 17th International Conference on VLSI Design. Proceedings..