W. Lur

Advanced 0.25-0.18 /spl mu/m fully-planarized 6-level-interconnect CMOS technology for foundry manufacturing

W. K. Yeh, T. Lin, C. Chen, 1998, 1998 Semiconductor Manufacturing Technology Workshop (Cat. No.98EX133).

A novel 0.25 /spl mu/m shallow trench isolation technology

S.W. Sun, W. Lur, S. Sun, 1996, International Electron Devices Meeting. Technical Digest.

The investigation of electroplating deposited copper films for advanced VLSI interconnection

W. Lur, Ming-Sheng Yang, H. C. Chen, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

S.Y. Hsu, S.W. Sun, M.J. Tsai, 1997, International Electron Devices Meeting. IEDM Technical Digest.