Jonghyuck Choi

A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

Hyungsoo Kim, Chulwoo Kim, J. Chun, 2021, IEEE Journal of Solid-State Circuits.

23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Hankyu Chi, Dongkyun Kim, Changhyun Lee, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Dongkyun Kim, Minsu Park, Mingyu Park, 2020, IEEE Journal of Solid-State Circuits.

A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector

Chulwoo Kim, Hyunsu Park, Jincheol Sim, 2023, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

Chulwoo Kim, Hyunsu Park, Jincheol Sim, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.