Nattapol Damrongplasit

Threshold Voltage and DIBL Variability Modeling Based on Forward and Reverse Measurements for SRAM and Analog MOSFETs

Luis Zamudio, Tsu-Jae King Liu, Sriram Balasubramanian, 2015, IEEE Transactions on Electron Devices.

Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield

Tsu-Jae King Liu, Yi-Bo Liao, Meng-Hsueh Chiang, 2014, IEEE Transactions on Electron Devices.

Impact of Gate Line-Edge Roughness (LER) Versus Random Dopant Fluctuations (RDF) on Germanium-Source Tunnel FET Performance

Sung Hwan Kim, Changhwan Shin, Nattapol Damrongplasit, 2013, IEEE Transactions on Nanotechnology.

Comparative Study of Uniform Versus Supersteep Retrograde MOSFET Channel Doping and Implications for 6-T SRAM Yield

Nuo Xu, Robert J. Mears, Hideki Takeuchi, 2013, IEEE Transactions on Electron Devices.

4H-SiC N-Channel JFET for Operation in High-Temperature Environments

Albert P. Pisano, Nattapol Damrongplasit, Debbie G. Senesky, 2014, IEEE Journal of the Electron Devices Society.

Comparison of 10 nm GAA vs. FinFET 6-T SRAM performance and yield

Yi-Bo Liao, Meng-Hsueh Chiang, Wei-Chou Hsu, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).