S. Watanabe

Dips computer complex featuring 100 mb/s optical fiber rings

S. Watanabe, T. Noshiko, 1987 .

Offset compensating bit-line sensing scheme for high density DRAMs

D. Takashima, T. Hara, S. Watanabe, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

A 45 ns 16 Mb DRAM with triple-well structure

S. Watanabe, J. Kumagai, S. Yoshikawa, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.