Mark G. Johnson

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

Thomas H. Lee, Matthew P. Crowley, Mark G. Johnson, 2003 .

Delay loop circuit for adjusting a clock delay

Yiu-Fai Chan, Thomas H. Lee, Kevin S. Donnelly, 1998 .

An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier

Mark G. Johnson, Mark Johnson, 1993 .

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

Thomas H. Lee, John T. Ho, Jared L. Zerbe, 1994, IEEE J. Solid State Circuits.

A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

Thomas H. Lee, T. Ishikawa, John T. Ho, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

Circuit with a delay locked loop to adjust the clock delay

Yiu-Fai Chan, Jun Kim, Thomas H. Lee, 1998 .

16.4 512Mb PROM with 8 Layers of Antifuse/Diode Cells

Michael Farmwald, Matthew P. Crowley, Mark G. Johnson, 2003 .

A 2 . 5 V CMOS Delay-Locked Loop for an 18 Mbit , 500 Megabytek DRAM

Jared Zerbe, Mark G. Johnson, Thomas H. Lee, 2004 .