Bendik Kleveland

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

Thomas H. Lee, Matthew P. Crowley, Mark G. Johnson, 2003 .

Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design"

S. Simon Wong, Thomas H. Lee, D. Vook, 2002 .

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency

Jae Choi, Ming Liu, Ben Lee, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

Mahmudul Hassan, Khaldoon Abugharbieh, Chethan Rao, 2014 .

An Intelligent RAM with Serial I/Os

Ming Liu, Mike Morrison, Jay Patel, 2013, IEEE Micro.

Nozzle Extraction Geo eta1 Atomizer Computer Simulation of

Wamadeva Balachandran, Bendik Kleveland, Srba R. Cvetkovic, 1996 .

High-frequency characterization of on-chip digital interconnects

Robert W. Dutton, Mark Horowitz, Xiaoning Qi, 2002, IEEE J. Solid State Circuits.

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Ming Liu, Ben Lee, Ashish Dixit, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

16.4 512Mb PROM with 8 Layers of Antifuse/Diode Cells

Michael Farmwald, Matthew P. Crowley, Mark G. Johnson, 2003 .