Pei-Ying Du

发表

Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Chih-Yuan Lu, Hang-Ting Lue, Wei-Chen Chen, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface

Chih-Yuan Lu, Nan-Tzu Lian, Tahone Yang, 2010, 2010 IEEE International Reliability Physics Symposium.

A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Study of Self-Healing 3D NAND Flash with Micro Heater to Improve the Performances and Lifetime for Fast NAND in NVDIMM Applications

Chih-Yuan Lu, Hung-Sheng Chang, Roger Lo, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

Read Disturb Evaluations of 3D NAND Flash for Highly Read-Intensive Edge-Computing Inference Device for Artificial Intelligence Applications

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

A study of barrier engineered Al2O3 and HfO2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness

Chih-Yuan Lu, Yung-Tai Hung, Hang-Ting Lue, 2010, 2010 IEEE International Memory Workshop.

Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle

Chih-Yuan Lu, Roger Lo, Hang-Ting Lue, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2016, 2016 IEEE Symposium on VLSI Technology.

A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Study of Intra-Nitride Charge Transport of SONOS-Type Devices using Gate-Sensing and Channel-Sensing Transient Analysis Method

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2013, 2013 Symposium on VLSI Technology.

Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2010, IEEE Transactions on Device and Materials Reliability.

Study of the charge-trapping characteristics of silicon-rich nitride thin films using the gate-sensing and channel-sensing (GSCS) method

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2009, 2009 IEEE International Reliability Physics Symposium.

Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Study of Thyristor-Mode Dual-Channel NAND Flash Devices

Tuo-Hung Hou, Wei-Chen Chen, Roger Lo, 2018, 2018 IEEE International Memory Workshop (IMW).

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2008, IEEE Transactions on Device and Materials Reliability.

The impact of melting during reset operation on the reliability of phase change memory

Chung Lam, Jing Li, Yu Zhu, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

An Approach of 3D NAND Flash Based Nonvolatile Computing-In-Memory (nvCIM) Accelerator for Deep Neural Networks (DNNs) with Calibration and Read Disturb Analysis

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2020, 2020 IEEE International Memory Workshop (IMW).

Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture

Chih-Yuan Lu, Hang-Ting Lue, Kuang-Yeu Hsieh, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A critical review of charge-trapping NAND flash devices

Yi-Hsuan Hsiao, Hang-Ting Lue, Tzu-Hsuan Hsu, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space

Yi-Hsuan Hsiao, Hang-Ting Lue, Chih-Yuan Lu, 2013, 2013 IEEE International Electron Devices Meeting.

Increasing VG-type 3D NAND flash cell density by using ultra-thin poly-silicon channels

Tahone Yang, Ya-Chin King, Hang-Ting Lue, 2013, 2013 5th IEEE International Memory Workshop.

Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage

Yi-Hsuan Hsiao, Hang-Ting Lue, Chih-Chang Hsieh, 2012, 2012 International Electron Devices Meeting.

A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability

Kuo-Pin Chang, Tahone Yang, Y. J. Chen, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

Min-Feng Hung, Kuo-Pin Chang, Roger Lo, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Understanding barrier engineered charge-trapping NAND flash devices with and without high-K dielectric

Rich Liu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2009, 2009 IEEE International Reliability Physics Symposium.

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

Tiao-Yuan Huang, Hang-Ting Lue, Kuang-Yeu Hsieh, 2008, IEEE Transactions on Electron Devices.

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method—Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

Rich Liu, Hang-Ting Lue, Kuang-Yeu Hsieh, 2008, IEEE Transactions on Electron Devices.

Study of Charge Trapping Vertical Location and Capture Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method

Hang-Ting Lue, Kuang-Yeu Hsieh, Pei-Ying Du, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.