Nicolas Mäding

The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor

Juergen Pille, Jens Leenstra, Stefan Büttner, 2006, Proceedings of the Design Automation & Test in Europe Conference.

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor

Hans-Joachim Wunderlich, Christian G. Zoellin, Jens Leenstra, 2006, 2006 IEEE International Test Conference.

IBM POWER6 accelerators: VMX and DFU

Eric M. Schwarz, Silvia M. Müller, Christian Jacobi, 2007, IBM J. Res. Dev..

Scan Test Planning for Power Reduction

Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Scan chain clustering for test power reduction

Hans-Joachim Wunderlich, Michael E. Imhof, Melanie Elm, 2008, 2008 45th ACM/IEEE Design Automation Conference.