Rolf Sautter

The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor

Juergen Pille, Jens Leenstra, Stefan Büttner, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology

Juergen Pille, G. Sapp, Michael Kugel, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction

Juergen Pille, Shankar Kalyanasundaram, Michael Kugel, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 1.8-GHz instruction window buffer for an out-of-order microprocessor core

Wolfram Sauer, Rolf Sautter, Jens Leenstra, 2001 .

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

Juergen Pille, Martin Eckert, Otto Wagner, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Carry network for a Übertragauswahladdiereinheit with balanced delay between forwarding and generating path

Dieter Wendel, Holger Wetter, Rolf Sautter, 2002 .

A 32nm 0.5V-supply dual-read 6T SRAM

Kevin J. Nowka, Sudesh Saroop, Sani R. Nassif, 2010, IEEE Custom Integrated Circuits Conference 2010.

Read / write port calibration scheme for reduction in multiple-port SRAM cells

Jens Leenstra, Dieter Wendel, Rolf Sautter, 2001 .