M. Revathy

A regular and improved representation for signed digit constant vector multiplication

S. Lavanya, M. Revathy, 2018 .

Implementation of a low power LDPC decoder using bit serial architecture

R. Saravanan, M. Revathy, R. Saravanan, 2014, International Conference on Information Communication and Embedded Systems (ICICES2014).

Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI

R. Saravanan, M. Revathy, 2012 .

Efficient author community generation on Nlp based relevance feature detection

Minu Lalitha Madhavu, M. Revathy, 2017, 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT).

Optimally Flexible Energy Conserving Protocol for Connectionless Oriented Systems

R. Kalaimagal, M. Revathy, 2015 .

Error detection and correction using decimal matrix code: Survey

M. Revathy, T. Evangeline Santhia, R. Helen Ramya Bharathi, 2017, 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE).

A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

R. Saravanan, M. Revathy, R. Saravanan, 2015, TheScientificWorldJournal.

Harvard architecture based post processed True random number generator

M. Revathy, M. Saranya, A. Kaleel Rahuman, 2021 .

Steganographic Techniques of Data Hiding using Digital Images

K. Sivasankari, M. Revathy, A. Komathi, 2015 .