Yoshiyuki Ishigaki

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

H. Honda, Tomohisa Wada, Kenji Anami, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

H. Honda, Kenji Anami, Toru Shiomi, 1993 .

A 5‐ns 32 K ×8/×9 bi‐CMOS TTL SRAM with alternated bit line load architecture

Hiroki Honda, Tadashi Sumi, Masahiro Ishida, 1994 .

SRAM semiconductor memory device

Yasuhiro Fujii, Yoshiyuki Ishigaki, 1998 .

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

S. Takano, S. Kayano, H. Honda, 1991 .

A method of manufacturing an SRAM semiconductor device having rectangular gate wiring elements

Shigeki Ohbayashi, Yoshiyuki Ishigaki, Hidemoto Tomita, 2002 .

A semiconductor memory device and method of manufacturing the same

Shigeki Ohbayashi, Yoshiyuki Ishigaki, Hidemoto Tomita, 2002 .

A 256‐K Bi‐CMOS ECL self‐timed RAM using merged Bi‐nMOS gates

Hiroki Honda, Tadashi Sumi, Kimio Suzuki, 1992 .

A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

Toru Shiomi, Shigeki Ohbayashi, Yoshiyuki Ishigaki, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.