Bechir Ayari

Retiming for BIST-sequential circuits

Bozena Kaminska, Samir Lejmi, Bechir Ayari, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Test Cycle Count Reduction in a Parallel Scan BIST Environment

Prab Varma, Bechir Ayari, 1998 .

A new dynamic test vector compaction for automatic test pattern generation

Bozena Kaminska, Bechir Ayari, B. Kaminska, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test Cycle Count Reduction in a Parallel Scan BIST Environment

Prab Varma, Bechir Ayari, P. Varma, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Automatic test vector generation for mixed-signal circuits

Bozena Kaminska, Naim Ben-Hamida, Bechir Ayari, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

Bozena Kaminska, Samir Lejmi, Bechir Ayari, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits

Bozena Kaminska, Samir Lejmi, Bechir Ayari, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Testing of embedded A/D converters in mixed-signal circuit

Bozena Kaminska, Naim Ben-Hamida, Bechir Ayari, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

BDD FTEST: fast, backtrack-free test generator based on binary decision diagram representation

Bozena Kaminska, Bechir Ayari, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.