S. Saito

A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifier

S. Shinozaki, O. Ozawa, Kenji Natori, 1986 .

A low-power sub 100 ns 256K bit dynamic RAM

K. Natori, T. Tanaka, S. Saito, 1983, IEEE Journal of Solid-State Circuits.

A 1024-bit MNOS RAM using avalanche-tunnel injection

N. Endo, I. Nojima, M. Konaka, 1975, IEEE Journal of Solid-State Circuits.

A 1Mb CMOS DRAM with fast page and static column modes

S. Shinozaki, O. Ozawa, Kenji Natori, 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.