K. Uchimura

A 1M synapse self-learning digital neural network chip

O. Saito, K. Aihara, O. Fujita, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A sparse memory-access neural network engine with 96 parallel data-driven processing units

Osamu Fujita, K. Aihara, K. Uchimura, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

Self-learning neural network LSI with high-resolution non-volatile analog memory

T. Morie, K. Uchimura, Osamu Fujita, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

An 8 G connections-per-second 54 mW digital neural network chip low-power chain-reaction architecture

Osamu Saito, K. Uchimura, Y. Amemiya, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A high-speed digital neural network chip with low-power chain-reaction architecture

Y. Amemiya, Osamu Saito, K. Uchimura, 1992 .

A digital neural network LSI using sparse memory access architecture

Osamu Fujita, K. Aihara, K. Uchimura, 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

A 16b oversampling A/D conversion technology using triple integration noise shaping

Y. Matsuya, K. Uchimura, A. Iwata, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.