T. Mourier

3D Integration challenges today from technological toolbox to industrial prototypes

T. Magis, C. Laviron, A. Charpentier, 2013, 2013 IEEE International Interconnect Technology Conference - IITC.

3D integration for power MOS H bridge power application

K. Pressel, R. Franiatte, T. Mourier, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

T. Mourier, Xavier Gagnard, X. Gagnard, 2010 .

LÉTI'S TWO STEP APPROACH IN THE DOMAIN OF 3D INTEGRATION

David Henry, Nicolas Sillon, T. Mourier, 2011 .

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

T. Magis, C. Laviron, A. Farcy, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Yves Morand, Christian Arvet, T. Mourier, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

Study of low temperature MOCVD deposition of TiN barrier layer for copper diffusion in high aspect ratio through silicon vias

Sylvain Maitrejean, Daniel Mathiot, Chris E. Jones, 2014 .

Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias

C. Aumont, T. Mourier, C. Ribiere, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Integration of Cu/SiOC in dual damascene interconnect for 0.1 /spl mu/m technology using a new SiC material as dielectric barrier

J. Cluzel, Lucile Arnaud, O. Louveau, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Investigation of the interface stability in HfO 2 -metal electrodes

Sylvain Maitrejean, Bernard Guillaumot, T. Mourier, 2003 .