S. Minoret

3D Integration challenges today from technological toolbox to industrial prototypes

T. Magis, C. Laviron, A. Charpentier, 2013, 2013 IEEE International Interconnect Technology Conference - IITC.

Investigations of titanium nitride as metal gate material, elaborated by metal organic atomic layer deposition using TDMAT and NH3

Sylvain Maitrejean, Bernard Guillaumot, S. Minoret, 2005 .

Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

R. Anciant, N. Sillon, D. Henry, 2009, 2009 11th Electronics Packaging Technology Conference.

Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias

C. Aumont, T. Mourier, C. Ribiere, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Passivated TiN nanocrystals/SiN trapping layer for enhanced erasing in nonvolatile memory

D. Lafond, P. Brianceau, Thierry Baron, 2010 .

Platinum silicide metallic source & drain process optimization for FDSOI pMOSFETs

M. Vinet, D. Lafond, F. Allain, 2009, 2009 IEEE International SOI Conference.

Comparative study of non-polar switching behaviors of NiO- and HfO2-based oxide resistive-RAMs

G. Auvert, L. Perniola, Andrea Fantini, 2011 .

Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width

X. Garros, O. Faynot, F. Andrieu, 2006, 2006 International Electron Devices Meeting.

Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 “high k” and 2 metal deposition techniques

X. Garros, Laurent Vandroux, Pascal Besson, 2007 .

Through Silicon Via technology using tungsten metallization

P. Brianceau, R. Anciant, N. Sillon, 2011, 2011 IEEE International Conference on IC Design & Technology.