Saptarsi Das

REDEFINE: Runtime reconfigurable polymorphic ASIC

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, TECS.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, J. Syst. Archit..

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Compiling HPC Kernels for the REDEFINE CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields

S. K. Nandy, Ranjani Narayan, Saptarsi Das, 2011, ICETE.

A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture

Ranjani Narayan, S. K. Nandy, Saptarsi Das, 2012 .

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2017, Integr..

A method for flexible reduction over binary fields using a field multiplier

S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan, 2011, Proceedings of the International Conference on Security and Cryptography.

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture

Masahiro Fujita, S. K. Nandy, Ranjani Narayan, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, CASES '09.

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Flexible resource allocation and management for application graphs on ReNÉ MPSoC

Ranjani Narayan, Anuj Rao, Saptarsi Das, 2016, PARMA-DITAM '16.

A Systolic Dataflow Based Accelerator for CNNs

Arnab Roy, Ankur Deshwal, Saptarsi Das, 2020, International Symposium on Circuits and Systems.

Transport Triggered near Memory Accelerator for Deep Learning

Kavitha T. Madhu, Ankur Deshwal, Abhishek Tyagi, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).