M. Hane

发表

Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation

K. Kumagai, Y. Kawakami, M. Hane, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

SRAM critical yield evaluation based on comprehensive physical / statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations

T. Fukai, M. Hane, M. Miyamura, 2007, 2007 IEEE Symposium on VLSI Technology.

Enhanced drivability of high-Vbd dual-oxide-based complementary BEOL-FETs for compact on-chip pre-driver applications

M. Hane, N. Inoue, Y. Hayashi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Statistical Compact Model Parameter Extraction by Direct Fitting to Variations

K. Takeuchi, M. Hane, 2008, IEEE Transactions on Electron Devices.

Analyses and optimization of strained-SiGe on Si pMOSFETs by using full-band device simulation

K. Takeuchi, M. Hane, M. Kawada, 2006, 2009 Symposium on VLSI Technology.

26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structure

T. Hase, M. Hane, K. Yako, 2006, 2009 Symposium on VLSI Technology.

Practical finFET design considering GIDL for LSTP (low standby power) devices

K. Takeuchi, M. Hane, K. Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Dynamic-clustering And Grain-growth Kinetics Effects On Dopant Diffusion In Polysilicon

M. Hane, S. Hasegawa, 1993, [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD).

J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

A. Amerasekera, H. Masuda, S.-W. Lee, 2007, 2007 IEEE Symposium on VLSI Technology.

High-voltage complementary BEOL-FETs on Cu interconnects using N-type IGZO and P-type SnO dual oxide semiconductor channels

S. Saito, M. Hane, Y. Hayashi, 2013, 2013 Symposium on VLSI Technology.

Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration

M. Hane, K. Uejima, H. Nakamura, 2007, 2007 IEEE Symposium on VLSI Technology.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

T. Fukai, T. Takeuchi, T. Iwamoto, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level

S. Kumashiro, M. Hane, Y. Tosaka, 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

M. Hane, N. Inoue, Y. Hayashi, 2011, 2011 International Electron Devices Meeting.

Investigation of realistic dopant fluctuation induced device characteristics variation for sub-100 nm CMOS by using atomistic 3D process/device simulator

M. Hane, T. Ikezawa, M. Hane, 2002, Digest. International Electron Devices Meeting,.

A Highly Efficient Statistical Compact Model Parameter Extraction Scheme

K. Takeuchi, M. Hane, 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.

Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches

M. Hane, Y. Hayashi, H. Sunamura, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs]

M. Hane, T. Ikezawa, T. Ezaki, 2003, IEEE International Electron Devices Meeting 2003.

Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction

T. Nagumo, S. Shishiguchi, M. Hane, 2007, 2007 IEEE International Electron Devices Meeting.

A new comprehensive SRAM soft-effor simulation based on 3D device simulation incorporating neutron nuclear reactions

M. Hane, K. Kumagai, H. Nakamura, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

Coupled Si and SiO/sub 2/ Monte Carlo device simulator for accurate gate current calculation

M. Hane, T. Ezaki, H. Nakasato, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

H. Kawaura, H. Wakabayashi, M. Hane, 2006, IEEE Transactions on Electron Devices.

Coupled atomistic 3D process/device simulation considering both line-edge roughness and random-discrete-dopant effects

M. Hane, T. Ikezawa, T. Ezaki, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

High on/off-ratio P-type oxide-based transistors integrated onto Cu-interconnects for on-chip high/low voltage-bridging BEOL-CMOS I/Os

M. Hane, Y. Hayashi, H. Sunamura, 2012, 2012 International Electron Devices Meeting.

Transport properties of sub-10-nm planar-bulk-CMOS devices

H. Kawaura, H. Wakabayashi, K. Takeuchi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..