M.H. Tsai

A new CVD tungsten nitride diffusion barrier for Cu interconnection

S.C. Sun, M.H. Tsai, H.T. Chiu, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Implement of an Improvement Particle Monitoring Methodology in an Industry Production Process

Po-Ying Chen, M.H. Tsai, M.H. Jing, 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.

A single-chip RF transceiver for quad-band GSM/GPRS applications

Hongxi Xue, L.W. Ke, G.K. Dehng, 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

High performance/reliability Cu interconnect with selective CoWP cap

M.S. Liang, M.H. Tsai, W.S. Shue, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2006, 2009 Symposium on VLSI Technology.

Effect of Cu Line Capping Process on Stress Migration Reliability

C.H. Yu, M.H. Tsai, W.S. Shue, 2006, 2006 International Interconnect Technology Conference.

Design of ECP additive for 65 nm-node technology Cu BEOL reliability

C.H. Yu, M.H. Tsai, W.S. Shue, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..