Yun Chiu

发表

A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR

Seung-Chul Lee, Yun Chiu, 2014, IEEE Journal of Solid-State Circuits.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

Wenbo Liu, Yun Chiu, Pingli Huang, 2011, IEEE Journal of Solid-State Circuits.

Digital Adaptive Calibration of Data Converters Using Independent Component Analysis

Yun Chiu, Y. Chiu, 2015 .

Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier

Dae Hyun Kwon, Yun Chiu, Hao Li, 2010, IEEE Journal of Solid-State Circuits.

Digitally-assisted design of data converters

Yun Chiu, 2015 .

Background digital calibration of successive approximation adc with adaptive equalisation

Yun Chiu, W. Liu, 2009 .

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

Yuan Zhou, Yun Chiu, Benwei Xu, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A motion-artifact tracking and compensation technique for dry-contact EEG monitoring system

Yun Chiu, Shuang Zhu, Jingyi Song, 2014, 2014 IEEE Signal Processing in Medicine and Biology Symposium (SPMB).

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

Yun Chiu, Yuan Zhou, Benwei Xu, 2019, IEEE Journal of Solid-State Circuits.

28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation

Yun Chiu, Sudipta Sarkar, Hai Huang, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer

Yun Chiu, Hai Huang, Ling Du, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation

Dae Hyun Kwon, Hao Li, Deming Chen, 2009, IEEE Journal of Selected Topics in Signal Processing.

A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling

Dae Hyun Kwon, Hao Li, Yun Chiu, 2010, IEEE Journal of Solid-State Circuits.

15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS

Yun Chiu, Shuang Zhu, Benwei Xu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

On the Operation of CMOS Active-Cascode Gain Stage

Yun Chiu, Y. Chiu, 2013 .

A 15 MHz to 600 MHz, 20 mW, 0.38 mm $^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$ m CMOS

Borivoje Nikolic, Yun Chiu, Sebastian Hoyos, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

24-GHz low noise amplifier using coplanar waveguide series feedback in 130-nm CMOS

Yun Chiu, Milton Feng, Giang D. Nguyen, 2009, 2009 Asia Pacific Microwave Conference.

A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3

Yun Chiu, Bo Wu, Y. Chiu, 2015, IEEE Journal of Solid-State Circuits.

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS

Borivoje Nikolic, Yun Chiu, Paul R. Gray, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers

Yun Chiu, Ada S. Y. Poon, Richard Tseng, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system

Yuan Zhou, Yun Chiu, Shuang Zhu, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over −80-dB IM3

Yun Chiu, Peiyuan Wan, Pingfen Lin, 2010, IEEE Custom Integrated Circuits Conference 2010.

Equalization techniques for nonlinear analog circuits

Yun Chiu, 2011, IEEE Communications Magazine.

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS

Yuan Zhou, Yun Chiu, Jingbo Ye, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

Borivoje Nikolic, Yun Chiu, Paul R. Gray, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs

Yun Chiu, Pingli Huang, 2007, 2007 IEEE International Symposium on Circuits and Systems.

25.4 A 1.8V 14b 10MS/s Pipelined ADC in 0.18µm CMOS with 99dB SFDR

Borivoje Nikolic, Yun Chiu, Paul R. Gray, 2004 .

A mixed-signal MIMO beamforming receiver

Yun Chiu, R. Tseng, A.S.Y. Poon, 2008, 2008 IEEE Radio and Wireless Symposium.

PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC

Yuan Zhou, Yun Chiu, Sudipta Sarkar, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration

Guanhua Wang, Yun Chiu, Foti Kacani, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices

Yun Chiu, Shuang Zhu, Tuo Shan, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Demystifying Bilateral Feedback Analysis (Invited)

Yun Chiu, Yu-him. Chiu, 2012 .

A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM

Yun Chiu, Shuang Zhu, Benwei Xu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM

Yun Chiu, Shuang Zhu, Benwei Xu, 2016, IEEE Journal of Solid-State Circuits.

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS

Yun Chiu, Benwei Xu, Yuan Zhou, 2017, IEEE Journal of Solid-State Circuits.

Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

Seung-Chul Lee, Yun Chiu, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS

Yuan Zhou, Yun Chiu, Benwei Xu, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

An ICA framework for digital background calibration of analog-to-digital converters

Yun Chiu, Wenbo Liu, Seung-Chul Lee, 2014 .

Advanced Digital Calibration Techniques for Data Converters

Yun Chiu, 2014 .

A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

Yun Chiu, Hai Huang, Brian Elies, 2017, IEEE Journal of Solid-State Circuits.

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration

Gin-Kou Ma, Wenbo Liu, Seung-Chul Lee, 2010, IEEE Custom Integrated Circuits Conference 2010.

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Yun Chiu, Shuang Zhu, Yongda Cai, 2018, IEEE Journal of Solid-State Circuits.

CMOS RF transmitter with integrated power amplifier utilizing digital equalization

Dae Hyun Kwon, Hao Li, Yun Chiu, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 2GS/s 8b flash ADC based on remainder number system in 65nm CMOS

Yun Chiu, Shuang Zhu, Yongda Cai, 2017, 2017 Symposium on VLSI Circuits.

An inherently linear phase-oversampling vector modulator in 90-nm CMOS

Dae Hyun Kwon, Hao Li, Yun Chiu, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration

Seung-Chul Lee, Yun Chiu, Brian Elies, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Direct-sequence maximum power-point tracker for photovoltaic sources

Yun Chiu, Xi Luo, 2010, 2010 Power and Energy Conference At Illinois (PECI).

A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS

Yuan Zhou, Yun Chiu, Ling Du, 2019, IEEE Journal of Solid-State Circuits.

Demystifying bilateral feedback analysis

Yun Chiu, Yu-him. Chiu, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Digital Calibration of Nonlinear Memory Errors in Sigma–Delta Modulators

Seung-Chul Lee, Yun Chiu, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An 85–225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS

Yun Chiu, Bo Wu, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Yuan Zhou, Yun Chiu, Benwei Xu, 2015, IEEE Journal of Solid-State Circuits.

A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector

Yun Chiu, P. Bhoraskar, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering

Guanhua Wang, Yun Chiu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Background calibration of time-interleaved ADC using direct derivative information

Yun Chiu, Benwei Xu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization

Wenbo Liu, Yun Chiu, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Analysis and Design of Pipeline Analog-to-Digital Converters

Yun Chiu, 2007 .

PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy

Yun Chiu, Sudipta Sarkar, Yuan Zhou, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters

Yun Chiu, Wenbo Liu, 2007, 2007 7th International Conference on ASIC.

A 24.7 mW 65 nm CMOS SAR-Assisted CT $\Delta\Sigma $ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR

Yun Chiu, Shuang Zhu, Benwei Xu, 2016, IEEE Journal of Solid-State Circuits.

Background ADC calibration in digital domain

Robert W. Brodersen, Borivoje Nikolic, Yun Chiu, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Inherently linear capacitor error-averaging techniques for pipelined A/D conversion

Yun Chiu, Y. Chiu, 2000 .

Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters

Yun Chiu, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration

Gin-Kou Ma, Wenbo Liu, Seung-Chul Lee, 2011, IEEE Journal of Solid-State Circuits.

A Digital Stochastic Gradient-Ascent Maximum Power-Point Tracking Technique for Photovoltaic Applications

Yun Chiu, Analog Professor, 2013 .

An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration

Yun Chiu, Sudipta Sarkar, Benwei Xu, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

Yun Chiu, Ling Du, Hai Huang, 2017, IEEE Journal of Solid-State Circuits.

Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC

Yun Chiu, Yuan Zhou, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS

Yuan Zhou, Yun Chiu, Shuang Zhu, 2018, IEEE Journal of Solid-State Circuits.

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters

Yun Chiu, Benwei Xu, Y. Chiu, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

Yun Chiu, Bei Peng, Hao Li, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

ICs : The Driver for Information Technology

Yun Chiu, Elyse Rosenbaum, Naresh R. Shanbhag, 2007 .

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

Man-Kay Law, Jeffrey S. Walling, Nagendra Krishnapura, 2021, IEEE J. Solid State Circuits.

A 1.2V, 10.8mW, 500kHz Sigma-Delta Modulator with 84dB SNDR and 96dB SFDR

Yun Chiu, B. Nikolic, C.W. Tsang, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

High-speed, high-resolution, radiation-tolerant SAR ADCs for particle physics experiments

Yun Chiu, Jingbo Ye, D. Gong, 2015 .