Jabulani Nyathi

发表

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Jabulani Nyathi, J.G. Delgado-Frias, J. Lowe, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

Poster Presentation 6: Logic Circuits Operating in Both Sub- and Above-Threshold Voltages

Jabulani Nyathi, Brent Bero, 2007, 2007 IEEE Workshop on Microelectronics and Electron Devices.

A wave-pipelined router architecture using ternary associative memory

Laxmi N. Bhuyan, José G. Delgado-Frias, Jabulani Nyathi, 2000, ACM Great Lakes Symposium on VLSI.

Wave-Pipelining the Global Interconnect to Reduce the Associated Delays

Jabulani Nyathi, Jose G. Delgado-Frias, Ray Robert Rydberg, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

On the advantages of serial architectures for low-power reliable computations

Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Serial Addition: Locally Connected Architectures

Valeriu Beiu, Walid Ibrahim, Snorre Aunet, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Evaluation of CPU Utilization Under a Hardware-software Partitioned Enviroment (Migrating Software to Hardware)

Jabulani Nyathi, Clint Cole, Hsiang-Ling Jamie Lin, 2007, ESA.

Multiple clock domain synchronization for network on chip architectures

Partha Pratim Pande, Souradip Sarkar, Jabulani Nyathi, 2007, 2007 IEEE International SOC Conference.

A distributed FIFO scheme for on chip communication

José G. Delgado-Frias, Jabulani Nyathi, Ray Robert Rydberg, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A wave-pipelined CMOS associate router for communication switches

José G. Delgado-Frias, Jabulani Nyathi, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

The Vanishing Majority Gate Trading Power and Speed for Reliability

Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, 2005 .

A VLSI interconnection network router using a D-CAM with hidden refresh

José G. Delgado-Frias, Jabulani Nyathi, Douglas H. Summerville, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

Decoupled dynamic ternary content addressable memories

José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Efficient Key Update Scheme For Wireless Sensor Networks

Jabulani Nyathi, Kamini Prajapati, J. Nyathi, 2006, ICWN.

Femto Joule Switching for Nano Electronics

Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, 2006, IEEE International Conference on Computer Systems and Applications, 2006..

Logic Circuits Operating in Subthreshold Voltages

Jabulani Nyathi, Brent Bero, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

A High Performance, Low Area Overhead Carry Lookahead Adder

Jabulani Nyathi, James Levy, 2004, ESA/VLSI.

Performance of CNFET SRAM cells under diameter variation corners

Jabulani Nyathi, Jose G. Delgado-Frias, Zhe Zhang, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

CNTFET SRAM cell design with tolerance to metallic CNTs

Jabulani Nyathi, Jose G. Delgado-Frias, Zhe Zhang, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.