Avinoam Kolodny

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits

Avinoam Kolodny, Eby G. Friedman, Michael Sotman, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Maximum effective distance of on-chip decoupling capacitors in power distribution grids

Avinoam Kolodny, Eby G. Friedman, Radu M. Secareanu, 2006, GLSVLSI '06.

Routing Table Minimization for Irregular Mesh NoCs

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Ran Ginosar, Avinoam Kolodny, Salomon Beer, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Efficiency optimization of integrated DC-DC buck converters

Avinoam Kolodny, Eby G. Friedman, Gregory Sizikov, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Frameworks for Interconnect Optimization

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

Avinoam Kolodny, Israel Cidon, Rudy Beraha, 2011, Low Power Networks-on-Chip.

Crosstalk noise reduction in synthesized digital logic circuits

Avinoam Kolodny, O. Milter, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Future Directions in Interconnect Optimization

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Design and dynamic management of hierarchical NoCs

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2016, Microprocess. Microsystems.

Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing

Avinoam Kolodny, Isaac Keslassy, Eitan Zahavi, 2014, 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects.

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015, Integr..

Parallel vs. serial on-chip communication

Ran Ginosar, Avinoam Kolodny, Arkadiy Morgenshtein, 2008, SLIP '08.

Multistate Register Based on Resistive RAM

Avinoam Kolodny, Eby G. Friedman, Ravi Patel, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The design of a latency constrained, power optimized NoC for a 4G SoC

Avinoam Kolodny, Israel Cidon, Rudy Beraha, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

QoS architecture and design process for cost effective Network on Chip

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2004 .

Centralized Adaptive Routing for NoCs

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2010, IEEE Computer Architecture Letters.

Optimal resizing of bus wires in layout migration

Avinoam Kolodny, Shmuel Wimer, Shay Michaely, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits

Avinoam Kolodny, Eby G. Friedman, Michael Sotman, 2008, IEEE Trans. Very Large Scale Integr. Syst..

The Power of Priority: NoC Based Distributed Cache Coherency

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

Asynchronous Current Mode Serial Communication

Ran Ginosar, Avinoam Kolodny, Rostislav Dobkin, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimal bus sizing in migration of processor design

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2010, IEEE Trans. Very Large Scale Integr. Syst..

The Devolution of Synchronizers

Ran Ginosar, Avinoam Kolodny, Salomon Beer, 2010, 2010 IEEE Symposium on Asynchronous Circuits and Systems.

A Cost Effective Centralized Adaptive Routing for Networks-on-Chip

Avinoam Kolodny, Israel Cidon, Shmuel Wimer, 2011, 2011 14th Euromicro Conference on Digital System Design.

Interconnect power and delay optimization by dynamic programming in gridded design rules

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2010, ISPD '10.

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Nahalal: Cache Organization for Chip Multiprocessors

Uri C. Weiser, Idit Keidar, Avinoam Kolodny, 2007, IEEE Computer Architecture Letters.

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Avinoam Kolodny, Eby G. Friedman, Victoria Vishnyakov, 2012, Microelectron. J..

Thread allocation directed by performance-power tradeoff in NoC-based CMPs

Avinoam Kolodny, Israel Cidon, Yaniv Ben-Itzhak, 2010, 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel.

LinkDivision Multiplexing (LDM)forNetwork-on-Chip Links

Avinoam Kolodny, Arkadiy Morgenshtein, Ldm Concept, 2006 .

Multi-net Sizing and Spacing of Bundle Wires

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Gana: A novel low-cost conflict-free NoC architecture

Avinoam Kolodny, Israel Cidon, Eitan Zahavi, 2013, TECS.

Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study

Avinoam Kolodny, Israel Cidon, Rudy Beraha, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Threads vs. caches: Modeling the behavior of parallel workloads

Avi Mendelson, Uri C. Weiser, Idit Keidar, 2010, 2010 IEEE International Conference on Computer Design.

Energy metrics for power efficient crosslink and mesh topologies

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Best of both worlds: A bus enhanced NoC (BENoC)

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2010 .

Cost considerations in network on chip

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2004, Integr..

QNoC asynchronous router

Ran Ginosar, Avinoam Kolodny, Rostislav Dobkin, 2009, Integr..

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

Ran Ginosar, Avinoam Kolodny, Yevgeny Perelman, 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

Efficient Link Capacity and QoS Design for Network-on-Chip

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Fast asynchronous shift register for bit-serial communication

Ran Ginosar, Avinoam Kolodny, Rostislav Dobkin, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

Frequency dependent efficiency model of on-chip DC-DC buck converters

Avinoam Kolodny, Michael Zelikson, Gregory Sizikov, 2010, 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel.

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2013, 2013 Euromicro Conference on Digital System Design.

An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2006, 2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel.

Trace cache sampling filter

Avi Mendelson, Avinoam Kolodny, Michael Behar, 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

Logic operations in memory using a memristive Akers array

Eitan Yaakobi, Avinoam Kolodny, Jehoshua Bruck, 2014, Microelectron. J..

Aneffective technique forsimultaneous interconnect channel delayand noisereduction innanometer VLSIdesign

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2006 .

Link Division Multiplexing (LDM) for Network-on-Chip Links

Ran Ginosar, Avinoam Kolodny, Arkadiy Morgenshtein, 2006, 2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel.

Many-Core vs. Many-Thread Machines: Stay Away From the Valley

Avi Mendelson, Uri C. Weiser, Idit Keidar, 2009, IEEE Computer Architecture Letters.

Distributed adaptive routing for big-data applications running on Data Center Networks

Avinoam Kolodny, Isaac Keslassy, Eitan Zahavi, 2012, 2012 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

Links as a service (LaaS): Guaranteed tenant isolation in the shared cloud

Avinoam Kolodny, Isaac Keslassy, Ori Rottenstreich, 2015, 2016 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

Packet-level static timing analysis for NoCs

Avinoam Kolodny, Mattan Erez, Isaac Keslassy, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

Effective Radii of On-Chip Decoupling Capacitors

Avinoam Kolodny, Eby G. Friedman, Michael Sotman, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The era of many-modules SoC: revisiting the NoC mapping problem

Avinoam Kolodny, Israel Cidon, Daniel Sigalov, 2009, 2009 2nd International Workshop on Network on Chip Architectures.

Optimizing heterogeneous NoC design

Avinoam Kolodny, Israel Cidon, Yaniv Ben-Itzhak, 2012, SLIP '12.

Interconnect Bundle Sizing Under Discrete Design Rules

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-net Sizing and Spacing in General Layouts

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Uri C. Weiser, Avinoam Kolodny, Eby G. Friedman, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ACCMP-assymetric cluster chip-multiprocessing

Uri C. Weiser, Avinoam Kolodny, Tomer Y. Morad, 2004 .

Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud

Avinoam Kolodny, Isaac Keslassy, Ori Rottenstreich, 2019, IEEE Journal on Selected Areas in Communications.

Special Section on International Symposium on Networks-on-Chip (NOCS)

Avinoam Kolodny, Li-Shiuan Peh, 2009, IEEE Trans. Very Large Scale Integr. Syst..

Micro-modem - reliability solution for NoC communications

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs)

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

Interconnect-power dissipation in a microprocessor

Uri C. Weiser, Avinoam Kolodny, Nachum Shamir, 2004, SLIP '04.

Optimizing Read-Once Data Flow in Big-Data Applications

Uri C. Weiser, Avinoam Kolodny, Mattan Erez, 2017, IEEE Computer Architecture Letters.

Interconnect Aspects in Design Methodology and EDA Tools

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Asynchronous Bit-stream Compression (ABC)

Ran Ginosar, Avinoam Kolodny, Arkadiy Morgenshtein, 2006, 2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel.

Timing optimization in logic with interconnect

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2008, SLIP '08.

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization

Avinoam Kolodny, Israel A. Wagner, Arkadiy Morgenshtein, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Static timing analysis for modeling QoS in networks-on-chip

Avinoam Kolodny, Mattan Erez, Isaac Keslassy, 2011, J. Parallel Distributed Comput..

Network Delays and Link Capacities in Application-Specific Wormhole NoCs

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2007, VLSI Design.

Exploring the limits of GPGPU scheduling in control flow bound applications

Avi Mendelson, Avinoam Kolodny, Evgeny Bolotin, 2012, TACO.

Utilizing shared data in chip multiprocessors with the Nahalal architecture

Uri C. Weiser, Idit Keidar, Avinoam Kolodny, 2008, SPAA '08.

Timing-driven variation-aware nonuniform clock mesh synthesis

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2010, GLSVLSI '10.

Task Scheduling Based On Thread Essence and Resource Limitations

Uri C. Weiser, Avinoam Kolodny, Tomer Y. Morad, 2012, J. Comput..

Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training

Avinoam Kolodny, Daniel Soudry, Dotan Di Castro, 2015, IEEE Transactions on Neural Networks and Learning Systems.

Best of both worlds: A bus enhanced NoC (BENoC)

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

Design and modelling of network on chip interconnects using transmission lines

Avinoam Kolodny, David Goren, Anastasia Barger, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

The complexity of VLSI power-delay optimization by interconnect resizing

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2012, J. Comb. Optim..

Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors

Uri C. Weiser, Avinoam Kolodny, Tomer Y. Morad, 2010, 2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming.

Memristor-based IMPLY logic design procedure

Uri C. Weiser, Avinoam Kolodny, Eby G. Friedman, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Interconnect Optimization by Net Ordering

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2015 .

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2013, Integr..

Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology

Avinoam Kolodny, Noam Dolev, Avner Kornfeld, 2005, J. Circuits Syst. Comput..

TEAM: ThrEshold Adaptive Memristor Model

Uri C. Weiser, Avinoam Kolodny, Eby G. Friedman, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Average latency and link utilization analysis of heterogeneous wormhole NoCs

Avinoam Kolodny, Israel Cidon, Yaniv Ben-Itzhak, 2015, Integr..

Low Power Clock Network Design

Avinoam Kolodny, Eby G. Friedman, Ran Ginosar, 2011 .

Memristor-Based Multithreading

Uri C. Weiser, Avinoam Kolodny, Eby G. Friedman, 2014, IEEE Computer Architecture Letters.

Power efficient tree-based crosslinks for skew reduction

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2009, GLSVLSI '09.

The devolution of synchronizers

Avinoam Kolodny, Salomon Beer, Ran Ginosar, 2010 .

Handling global traffic in future CMP NoCs

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2012 .

On optimal ordering of signals in parallel wire bundles

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2008, Integr..

Handling global traffic in future CMP NoCs

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2012, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel.

Access Regulation to Hot-Modules in Wormhole NoCs

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

A clock tuning circuit for system–on–chip

Ran Ginosar, Avinoam Kolodny, Y. Elboim, 2002 .

QNoC: QoS architecture and design process for network on chip

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2004, J. Syst. Archit..

Performance scalability and dynamic behavior of Parsec benchmarks on many-core processors

Uri C. Weiser, Idit Keidar, Avinoam Kolodny, 2014 .

A clock tuning circuit for system–on–chip

Ran Ginosar, Avinoam Kolodny, Y. Elboim, 2003, Proceedings of the 28th European Solid-State Circuits Conference.

Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With $RC$ Interconnect

Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Designing single-cycle long links in hierarchical NoCs

Avinoam Kolodny, Israel Cidon, Ran Manevich, 2014, Microprocess. Microsystems.

EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems

Uri C. Weiser, Idit Keidar, Avinoam Kolodny, 2016, J. Parallel Distributed Comput..

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

Avinoam Kolodny, Israel A. Wagner, Arkadiy Morgenshtein, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic Programming Algorithm for Interconnect Channel Sizing in Discrete Design Rules

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2009 .

Efficient Routing in Irregular Topology NoCs

Ran Ginosar, Avinoam Kolodny, Israel Cidon, 2022 .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (

Avinoam Kolodny, Ravi Patel, Shahar Kvatinsky, 2014 .

On VLSI interconnect optimization and linear ordering problem

Avinoam Kolodny, Konstantin Moiseev, Shmuel Wimer, 2011 .

Two components of tunneling current in metal‐oxide‐semiconductor structures

Avinoam Kolodny, B. Eitan, B. Eitan, 1983 .

Power grid analysis based on a macro circuit model

Avinoam Kolodny, Eby G. Friedman, Shahar Kvatinsky, 2010, 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel.