Juan C. Peña Ramos

发表

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

Marcel J. M. Pelgrom, Marian Verhelst, Michiel S. J. Steyaert, 2020, IEEE Journal of Solid-State Circuits.